Lpc2000

Has anyone tested the IDCY delay between each access to external memory?

I'm using an octal uart from Philips witch need 100nsec between each
access (read or write type). The scoop shows only 32 nsec independent
off different values in IDCY. I'm running the controller at 60MHz.

 

  // Octal Uart chip select.

  BCFG2_bit.IDCY = 6;     // 16.66nsec * (6+1) = 116.6 nsec.  (Min
100nsec)

  BCFG2_bit.WST1 = 15;    // 15 * 16.66nsec = 250nsec wait states for
the SCC2698

  BCFG2_bit.WST2 = 15;    // 15 * 16.66nsec = 250nsec wait states for
the SCC2698

  BCFG2_bit.RBLE = 0;     // 8 Bit access using BLS0 as write enable.

  BCFG2_bit.WP = 0;       // Write protect off(0).

  BCFG2_bit.BM = 0;       // Burst rom bank off(0).

  BCFG2_bit.MW = 0;       // 8 bit(00) 16 bit(01) 32 bit(10)
reserved(11)

 

  Strb r8,[r7]                 // 

  Strb r8,[r7]                 // Scoop shows 32 nsec delay between each
access to external memory (valid for both CS and WR)

  Strb r8,[r7]                 // Not 116,6 nsec as expected?

  Strb r8,[r7]

 

Any idee?

 

Regards 

Sveinung



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