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IDCY LPC2294

2005-05-04 by Sveinung Waade

Has anyone tested the IDCY delay between each access to external memory?

I'm using an octal uart from Philips witch need 100nsec between each
access (read or write type). The scoop shows only 32 nsec independent
off different values in IDCY. I'm running the controller at 60MHz.

 

  // Octal Uart chip select.

  BCFG2_bit.IDCY = 6;     // 16.66nsec * (6+1) = 116.6 nsec.  (Min
100nsec)

  BCFG2_bit.WST1 = 15;    // 15 * 16.66nsec = 250nsec wait states for
the SCC2698

  BCFG2_bit.WST2 = 15;    // 15 * 16.66nsec = 250nsec wait states for
the SCC2698

  BCFG2_bit.RBLE = 0;     // 8 Bit access using BLS0 as write enable.

  BCFG2_bit.WP = 0;       // Write protect off(0).

  BCFG2_bit.BM = 0;       // Burst rom bank off(0).

  BCFG2_bit.MW = 0;       // 8 bit(00) 16 bit(01) 32 bit(10)
reserved(11)

 

  Strb r8,[r7]                 // 

  Strb r8,[r7]                 // Scoop shows 32 nsec delay between each
access to external memory (valid for both CS and WR)

  Strb r8,[r7]                 // Not 116,6 nsec as expected?

  Strb r8,[r7]

 

Any idee?

 

Regards 

Sveinung



[Non-text portions of this message have been removed]

Re: [lpc2000] IDCY LPC2294

2005-05-04 by Richard Duits

If I remember correctly, the IDCY only applies if you switch between 
reads and writes or if you access another memory bank.
So between 2 writes to the same bank there is no IDCY.

Richard.


Sveinung Waade wrote:

Show quoted textHide quoted text

>Has anyone tested the IDCY delay between each access to external memory?
>
>I'm using an octal uart from Philips witch need 100nsec between each
>access (read or write type). The scoop shows only 32 nsec independent
>off different values in IDCY. I'm running the controller at 60MHz.
>
>
>
>  // Octal Uart chip select.
>
>  BCFG2_bit.IDCY = 6;     // 16.66nsec * (6+1) = 116.6 nsec.  (Min
>100nsec)
>
>  BCFG2_bit.WST1 = 15;    // 15 * 16.66nsec = 250nsec wait states for
>the SCC2698
>
>  BCFG2_bit.WST2 = 15;    // 15 * 16.66nsec = 250nsec wait states for
>the SCC2698
>
>  BCFG2_bit.RBLE = 0;     // 8 Bit access using BLS0 as write enable.
>
>  BCFG2_bit.WP = 0;       // Write protect off(0).
>
>  BCFG2_bit.BM = 0;       // Burst rom bank off(0).
>
>  BCFG2_bit.MW = 0;       // 8 bit(00) 16 bit(01) 32 bit(10)
>reserved(11)
>
>
>
>  Strb r8,[r7]                 //
>
>  Strb r8,[r7]                 // Scoop shows 32 nsec delay between each
>access to external memory (valid for both CS and WR)
>
>  Strb r8,[r7]                 // Not 116,6 nsec as expected?
>
>  Strb r8,[r7]
>
>
>
>Any idee?
>
>
>
>Regards
>
>Sveinung
>
>
>
>[Non-text portions of this message have been removed]
>
>
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RE: [lpc2000] IDCY LPC2294 (Shorted)

2005-05-04 by Sveinung Waade

Tanks Richard - that's verified and nearly true. I tested the following

  

// r7 and r8 points to the external memory

  ldrb r7,r[8]

  strb r8,r[7#0x1]

  ldrb r7,r[8]

  strb r8,r[7,#0x1]

  ldrb r7,r[8]

  strb r8,r[7,#0x1]

 

and got the following instruction transition result:

Ldrb-strb => no delay and within same chipselect.

Strb-ldrb => 100nsec delay (and different chipselect) as supposed.

 

There is not much information regarding this in the LPC User manual.

 Are there some documents that describe the EMC (external memory
controller) more in detail?

 

I am forced to control the read write access timing to the slow octal
uart manually in software since it require 100nsec between reads and/or
writes.

 

Sveinung.

Show quoted textHide quoted text

-----Original Message-----
From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf
Of Richard Duits
Sent: 4. mai 2005 14:21
To: lpc2000@yahoogroups.com
Subject: Re: [lpc2000] IDCY LPC2294

If I remember correctly, the IDCY only applies if you switch between 
reads and writes or if you access another memory bank.
So between 2 writes to the same bank there is no IDCY.

Richard.

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[Non-text portions of this message have been removed]

Re: [lpc2000] IDCY LPC2294 (Shorted)

2005-05-04 by Richard Duits

I did not find a way to guarentee an idle time between writes. I 
inserted an extra write to another address to insert the idle time. It 
is also nearly inpossible to get the setup time right for any signals 
that must be there on the falling edge of WE or BLS during a write cycle.

Richard.

Sveinung Waade wrote:

Show quoted textHide quoted text

> Tanks Richard - that's verified and nearly true. I tested the following
>
>  
>
> // r7 and r8 points to the external memory
>
>   ldrb r7,r[8]
>
>   strb r8,r[7#0x1]
>
>   ldrb r7,r[8]
>
>   strb r8,r[7,#0x1]
>
>   ldrb r7,r[8]
>
>   strb r8,r[7,#0x1]
>
>
>
> and got the following instruction transition result:
>
> Ldrb-strb => no delay and within same chipselect.
>
> Strb-ldrb => 100nsec delay (and different chipselect) as supposed.
>
>
>
> There is not much information regarding this in the LPC User manual.
>
> Are there some documents that describe the EMC (external memory
> controller) more in detail?
>
>
>
> I am forced to control the read write access timing to the slow octal
> uart manually in software since it require 100nsec between reads and/or
> writes.
>
>
>
> Sveinung.
>
> -----Original Message-----
> From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf
> Of Richard Duits
> Sent: 4. mai 2005 14:21
> To: lpc2000@yahoogroups.com
> Subject: Re: [lpc2000] IDCY LPC2294
>
>
>
> If I remember correctly, the IDCY only applies if you switch between
> reads and writes or if you access another memory bank.
> So between 2 writes to the same bank there is no IDCY.
>
> Richard.
>
>
>
>   _____ 
>
> Yahoo! Groups Links
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>
>
> [Non-text portions of this message have been removed]
>
>
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Lpc2000

IDCY LPC2294

IDCY LPC2294

Re: [lpc2000] IDCY LPC2294

RE: [lpc2000] IDCY LPC2294 (Shorted)

Re: [lpc2000] IDCY LPC2294 (Shorted)

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