Lpc2000

I did not find a way to guarentee an idle time between writes. I 
inserted an extra write to another address to insert the idle time. It 
is also nearly inpossible to get the setup time right for any signals 
that must be there on the falling edge of WE or BLS during a write cycle.

Richard.

Sveinung Waade wrote:

> Tanks Richard - that's verified and nearly true. I tested the following
>
>  
>
> // r7 and r8 points to the external memory
>
>   ldrb r7,r[8]
>
>   strb r8,r[7#0x1]
>
>   ldrb r7,r[8]
>
>   strb r8,r[7,#0x1]
>
>   ldrb r7,r[8]
>
>   strb r8,r[7,#0x1]
>
>
>
> and got the following instruction transition result:
>
> Ldrb-strb => no delay and within same chipselect.
>
> Strb-ldrb => 100nsec delay (and different chipselect) as supposed.
>
>
>
> There is not much information regarding this in the LPC User manual.
>
> Are there some documents that describe the EMC (external memory
> controller) more in detail?
>
>
>
> I am forced to control the read write access timing to the slow octal
> uart manually in software since it require 100nsec between reads and/or
> writes.
>
>
>
> Sveinung.
>
> -----Original Message-----
> From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf
> Of Richard Duits
> Sent: 4. mai 2005 14:21
> To: lpc2000@yahoogroups.com
> Subject: Re: [lpc2000] IDCY LPC2294
>
>
>
> If I remember correctly, the IDCY only applies if you switch between
> reads and writes or if you access another memory bank.
> So between 2 writes to the same bank there is no IDCY.
>
> Richard.
>
>
>
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