Lpc2000

Tanks Richard - that's verified and nearly true. I tested the following

  

// r7 and r8 points to the external memory

  ldrb r7,r[8]

  strb r8,r[7#0x1]

  ldrb r7,r[8]

  strb r8,r[7,#0x1]

  ldrb r7,r[8]

  strb r8,r[7,#0x1]

 

and got the following instruction transition result:

Ldrb-strb => no delay and within same chipselect.

Strb-ldrb => 100nsec delay (and different chipselect) as supposed.

 

There is not much information regarding this in the LPC User manual.

 Are there some documents that describe the EMC (external memory
controller) more in detail?

 

I am forced to control the read write access timing to the slow octal
uart manually in software since it require 100nsec between reads and/or
writes.

 

Sveinung.

-----Original Message-----
From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf
Of Richard Duits
Sent: 4. mai 2005 14:21
To: lpc2000@yahoogroups.com
Subject: Re: [lpc2000] IDCY LPC2294

 

If I remember correctly, the IDCY only applies if you switch between 
reads and writes or if you access another memory bank.
So between 2 writes to the same bank there is no IDCY.

Richard.



  _____  

Yahoo! Groups Links

*         To visit your group on the web, go to:
http://groups.yahoo.com/group/lpc2000/
  

*         To unsubscribe from this group, send an email to:
lpc2000-unsubscribe@yahoogroups.com
<mailto:lpc2000-unsubscribe@yahoogroups.com?subject=Unsubscribe> 
  

*         Your use of Yahoo! Groups is subject to the Yahoo! Terms of
<http://docs.yahoo.com/info/terms/>  Service. 



[Non-text portions of this message have been removed]