Lpc2000

Bob,

You are absolutely right.  The Errata has a note on it.  Jim E. of 
Philips was very helpful in pointing this out also.

So the moral of the story is:

P0.31 of the 2138 should only be used as an output and it must be 
high during reset or "device behaviour is undetermined".

Thanks for the help.

Michael

--- In lpc2000@yahoogroups.com, "lpc2100_fan" <lpc2100_fan@y...> 
wrote:
> Michael,
> 
> I did mean P0.31 not P1.31.  P0.31 is an output only pin but 
according
> to the information that I got, it gets sampled at reset and can
> generate weird things if it is low @ reset.
> 
> Bob
> 
> --- In lpc2000@yahoogroups.com, "michael_rubinstein_sar"
> <michael_rubinstein_sar@y...> wrote:
> > Hi Bob, thanks for the help.
> > 
> > I'll bet you meant 1.31 (\TRST).  This signal is not connected 
on 
> > our board.  However, it is driven high by the JTAG gizmo (J-
Link).
> > 
> > The other problems are really odd.  After an external reset, 
some of 
> > the I/O pins just don't work.  I tried disconnecting 0.18 from 
other 
> > circuitry, programming it as a gpio output and toggling it a few 
> > times.  It works as expected after a power-up but just stays low 
> > after an external reset.
> > 
> > My code doesn't know the difference between a power-up reset and 
an 
> > external reset.  I wonder if the ISP code behaves differently 
before 
> > it transfers control to my code.
> > 
> > Michael
> >  
> > 
> > --- In lpc2000@yahoogroups.com, "lpc2100_fan" <lpc2100_fan@y...> 
> > wrote:
> > > Hello Michael,
> > > 
> > > one possible reason although this might not seem related.  If 
you 
> > have
> > > an external signal on pin 0.31 that would drive this pin low 
during
> > > reset (no matter which reset), the LPC2138 will no longer 
enable 
> > the
> > > JTAG.  Please make sure that P0.31 not driven externally (has 
a 
> > weak
> > > pull-up) when any reset occurs. 
> > > 
> > > hth, Bob
> > > 
> > > 
> > > 
> > > --- In lpc2000@yahoogroups.com, "michael_rubinstein_sar"
> > > <michael_rubinstein_sar@y...> wrote:
> > > > I'm debugging a new 2138 based design.
> > > > 
> > > > If the board is powered up, eveything works as expected.  
> > However, if 
> > > > an external reset (\RESET) is then applied, several funny 
things 
> > happen:
> > > > 
> > > > o  JTAG stops working.
> > > > o  P0.18 which is configured as a timer capture input, sinks 
> > current.
> > > > o  P0.4 which is used as SPI SCK, in master mode, stops 
going 
> > high.
> > > > 
> > > > I verified the values in PINSEL, IODIR and IOSET.  They are 
> > correct and 
> > > > the same in both cases.
> > > > 
> > > > Any help appreciated.
> > > > 
> > > > Thanks,
> > > > Michael Rubinstein