Lpc2000

Hi Brian,

The document DDI0029_7TDMI_trm.pdf explains the minimum and maximum
interrupt latencies
in Section 2.9 for FIQs and IRQs, which is 5-29 cycles for time till entry
at the vector's first instruction.
The 29 cycles account for worst case LDM instruction that loads all
registers + PC (20 cycles in
Zero Wait State)

Someone very recently posted about a newer document I think that applies to
LPC2100.

-- Kris


> Does anyone have information on how many CPU cycles it takes to get into
> and out of a FIQ interrupt? Does it matter what interrupt triggered it?
> I'm trying to calculate interrupt overhead.
>
> Thanks,
>
> Brian
>
> --
> -----------------------------------------------------
> Brian C. Lane (W7BCL)                      Programmer
> www.shinemicro.com   RF, DSP & Microcontroller Design