Lpc2000

microbit wrote:
> Hi Brian,
> 
> The document DDI0029_7TDMI_trm.pdf explains the minimum and maximum
> interrupt latencies
> in Section 2.9 for FIQs and IRQs, which is 5-29 cycles for time till entry
> at the vector's first instruction.
> The 29 cycles account for worst case LDM instruction that loads all
> registers + PC (20 cycles in
> Zero Wait State)

I found DDI0234A_7TDMIS_R4.pdf from the ARM website (ARM7 TDMI-S core 
document) and it says the worst case is 27 cycles. Still haven't sorted 
out the return cycle count, it looks like it uses a SUB instruction?

> 
> Someone very recently posted about a newer document I think that applies to
> LPC2100.
> 

I'd be interested in seeing that as well.

Brian

-- 
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Brian C. Lane (W7BCL)                      Programmer
www.shinemicro.com   RF, DSP & Microcontroller Design