Lpc2000

--- In lpc2000@yahoogroups.com, "itsjustimpossible" <simonjh@b...> wrote:

    I would like to clarify your request.

> Hi
> There have been a few messages about this, but I can't find anything 
> explicit so I thought I would ask a quick question.
> 
> In an FIQ I need to transfer 15 bytes to an external device in less 
> than 1uS.
> 

   Does this mean :

   1) " Start transfering 15 with 1uS after the edge that causes FIQ"
   2) " Finish 15 bytes with in 1 uS after the edge that causes FIQ"


> Is this possible? Unless I am completely off track (probable), it 
> looks like it should be.
> 

   As you can see the timing of these two cases is very dramatic.


> The bus is 8-bit with no wait states. We are using the PLL to give a 
> 60MHz core clock and the peripheral clock is set equal to the core 
> clock. The MAM is enabled.
> 
> I can't seem to achieve anywhere near this figure.
> 
> Any thoughts would be greatly appreciated.
> 
> many thanks
> Simo


Thanks

donhamilton