Lpc2000

Hi
Thanks for the suggestion but we already have it configured with zero 
wait states etc. So the bus should be running as fast as possible.

I have been doing some experiments today and I think the bus access is 
probably OK. I think the main source of delay is the interrupt latency 
of the FIQ which seems to be about 800nS.

There is also some jitter on that, so all together I am not sure if 
the ARM7 is capable of doing what I need in this instance.

Bit of a shame

Best regards
Simon

--- In lpc2000@yahoogroups.com, "k b shah \(lascaux\)" <kbshah@l...> 
wrote:
> Gentleman,
> look at your BCFG value. it determines our read/write and wait state 
and idle time between two  read/write ...
> You have to minimize this as you requirement is 15 byte per 
microsecond measns 66ns per byte time...
> k b shah