Lpc2000

We are using the 2106 as a SPI slave device with CPOL = 0, CPHA = 0, MSB.  We are able to 
always receive commands OK, but are having problems sending commands back.  If the 
master provides the SCLK at too SLOW of a rate, the data from the 2106 is shifted to the left 
by 1 after the fist byte sent back.  Having the master speed up the SCLK takes care of this 
problem and data sent from the 2106 on the MISO line is fine, however smaller processors 
are unable to provide a fast enough clock rate (bit banging).  Other than the SPI registers, are 
there any other registers (powering off other peripherals not being used) that should be set?

Thanks

Jay