Lpc2000

We are using the 2106 as a SPI slave device with CPOL = 0, CPHA = 0, MSB.  We are able to 
always receive commands OK, but are having problems sending commands back.  If the 
master provides the SCLK at too SLOW of a rate, the data from the 2106 is shifted to the left 
by 1 after the fist byte sent back.  Having the master speed up the SCLK takes care of this 
problem and data sent from the 2106 on the MISO line is fine, however smaller processors 
are unable to provide a fast enough clock rate (bit banging).  Other than the SPI registers, are 
there any other registers (powering off other peripherals not being used) that should be set?

Thanks

Jay

Hi Jay

It is interesting what you write. I intended using the LPC2106 in 
slave SPI mode a few months ago when interfacing it it to a 
Freescale NE64 as 100M LAN coprocessor. The data was always received 
by the LPC correctly but what it sent back was irregular. I 
eventually gave up and use it in Master mode concluding that the SPI 
has errors. In master mode there are no problems.

If you search the archives you should find my original message which 
give much more details.

I have an embedded web server running at http://212.254.22.36/ for 
test purposes if you are interested.

Cheers

Mark Butcher

www.mjbc.ch

--- In lpc2000@yahoogroups.com, "jay_pni" <jay_pni@y...> wrote:
> We are using the 2106 as a SPI slave device with CPOL = 0, CPHA = 
0, MSB.  We are able to 
> always receive commands OK, but are having problems sending 
commands back.  If the 
> master provides the SCLK at too SLOW of a rate, the data from the 
2106 is shifted to the left 
> by 1 after the fist byte sent back.  Having the master speed up 
the SCLK takes care of this 
> problem and data sent from the 2106 on the MISO line is fine, 
however smaller processors 
> are unable to provide a fast enough clock rate (bit banging).  
Other than the SPI registers, are 
> there any other registers (powering off other peripherals not 
being used) that should be set?

> 
> Thanks
> 
> Jay