Lpc2000

--- In lpc2000@yahoogroups.com, "genie_23432" <pascal_poirier@h...> 
wrote:
> --- In lpc2000@yahoogroups.com, "vajper0" <ph@w...> wrote:
> > I'm writing a driver for UART1 on a LPC2138. So far most things 
> seems
> > to work (considering the crappy hardware capabilities). My current
> > problem is that I loose interrupts when receiving data.
> > 
> > I run the UART in 115200bps and my ISR takes care of all IRQs 
except
> > the modem status ones that are not enabled. If I send a block of a
> > couple of hundreds characters, sometimes one RDA IRQ is lost. I 
know
> > this because the missing data always are the size of the Rx 
trigger 
> level.
> > 
> > The ISR reads the U1IIR once in the beginning, compares the 
register
> > data to the different IRQ types in priority order. The first 
> matching
> > type is handled (and the IRQ resetted), the U1IIR is then read 
again
> > and so on. When no more pending IRQs, the ISR is exited. When a 
> > 
> > Am I missing something essential?
> 
> I am also doing the same type of situation on a 2119.  When it 
works 
> it works great but when it doesn't well it just doesn't work.  
There 
> is errata on the UART1 for the 2119 but I should be working around 
> it.  I found that if I could send a continual stream of data and it 
> linked from the start it would usually work without issue.  If I 
> place the serial link after the fact it only seems to work 1/4 of 
the 
> time if that.
> 
> I wish I could be of more help to you other then to say you are not 
> the only one and I have been able to reproduce it on a LPC2119.  I 
am 
> very interested in hearing any possible solutions.

Added info I forgot to include.

In my case I find that the UART1 U1FCR bit FIFO Enable is often 
cleared randomly.  I also find that the U1FCR Tx FIFO Reset bit gets 
set high randomly, usually along with the clearing of the enable 
bit.  I have not been able to determine what is causing these bits to 
change since I only touch then in setup and to flush the receive FIFO 
if a receive error occurs (even without an error the still change).  
The UART usually seems to keep working after the fifo bit goes low 
but every time the UART does not work the FIFO enable bit does appear 
to be zero.

Anyone have any ideas on what I am doing wrong to cause the setup 
bits to change on their own?