There is no limit on PCLK, other than it can never exceed CCLK, because
of the divider. With XTAL=14.7M, the PLL set to 4 (CCLK= ~59M), the
VPB set to 1 gives you a maximum PCLK of ~59M.
As the manual states: all internal devices can deal with this speed just
fine; the reason for the VPN (and its default setting) is to conserve power
by not running at the highest possible speed.
--fred
g pf <radiotommy2000@...> wrote:
Yes, of couse. we have do this in my desing. It works
fine.
--- arkeryd <arkeryd@...>дµÀ:
---------------------------------
Hello to you all, doing my first post here...
The Philips LPC 21xx user manual carefully explains
about pclk <->
cclk relation and vpb divider, but doesn't say whether
there is any
upper limit on pclk...
Does anyone know if pclk can safely run at same speed
as cclk (vpb
divider=1), even if cclk is set at max, that is 60mhz
on the LPC 2119
version I am using?
Kind Regards
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[Non-text portions of this message have been removed]Message
Re: »Ø¸´£º [lpc2000] vpb divider when cpu clock speed is at max...
2005-08-08 by DECwiz (Fred van Kempen)
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