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2005-08-05 by arkeryd
Hello to you all, doing my first post here... The Philips LPC 21xx user manual carefully explains about pclk <-> cclk relation and vpb divider, but doesn't say whether there is any upper limit on pclk... Does anyone know if pclk can safely run at same speed as cclk (vpb divider=1), even if cclk is set at max, that is 60mhz on the LPC 2119 version I am using? Kind Regards
2005-08-05 by philips_apps
--- In lpc2000@yahoogroups.com, "arkeryd" <arkeryd@y...> wrote: > Hello to you all, doing my first post here... > > The Philips LPC 21xx user manual carefully explains about pclk <-> > cclk relation and vpb divider, but doesn't say whether there is any > upper limit on pclk... > > Does anyone know if pclk can safely run at same speed as cclk (vpb > divider=1), even if cclk is set at max, that is 60mhz on the LPC 2119 > version I am using? > > Kind Regards Hello arkeryd@ There is no upper limit for the pclk frequency in the currently available LPC2000 microcontrollers. Regardless of the cclk value, you can safely have your pclk = cclk (VPBDIV = 0x01) and have pclk=60MHz. The reason why the pclk = cclk/4 at reset is to reduce an overall power consumption of the device. Regards, Philips Apps Team
2005-08-08 by g pf
Yes, of couse. we have do this in my desing. It works
fine.
--- arkeryd <arkeryd@...>\u0434\ufffd\ufffd:
---------------------------------
Hello to you all, doing my first post here...
The Philips LPC 21xx user manual carefully explains
about pclk <->
cclk relation and vpb divider, but doesn't say whether
there is any
upper limit on pclk...
Does anyone know if pclk can safely run at same speed
as cclk (vpb
divider=1), even if cclk is set at max, that is 60mhz
on the LPC 2119
version I am using?
Kind Regards
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\ufffd\u017b\ufffd\ufffd\ufffd\ufffdG\ufffd\ufffd\ufffd\u48ed\ufffd\u0439\ufffd\ufffd\ufffd\u04bb\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\u02bc\ufffd\u0267\ufffd\u0173\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd
http://cn.mail.yahoo.com/?id=770712005-08-08 by DECwiz (Fred van Kempen)
There is no limit on PCLK, other than it can never exceed CCLK, because
of the divider. With XTAL=14.7M, the PLL set to 4 (CCLK= ~59M), the
VPB set to 1 gives you a maximum PCLK of ~59M.
As the manual states: all internal devices can deal with this speed just
fine; the reason for the VPN (and its default setting) is to conserve power
by not running at the highest possible speed.
--fred
g pf <radiotommy2000@...> wrote:
Yes, of couse. we have do this in my desing. It works
fine.
--- arkeryd <arkeryd@...>дµÀ:
---------------------------------
Hello to you all, doing my first post here...
The Philips LPC 21xx user manual carefully explains
about pclk <->
cclk relation and vpb divider, but doesn't say whether
there is any
upper limit on pclk...
Does anyone know if pclk can safely run at same speed
as cclk (vpb
divider=1), even if cclk is set at max, that is 60mhz
on the LPC 2119
version I am using?
Kind Regards
---------------------------------
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