Lpc2000

On Wednesday 21 September 2005 10:27, David Hawkins wrote:
> Hey Michael,
>
> In your port os_cpu_a.S, you use the store/load-multiple
> instructions in your context save and restore routines, whereas
> in Jean Labrosse's versions he uses individual instructions.
>
> The comment made by Jean in one or more of his app notes runs
> along the lines that in User/System mode the store/load-multiple
> instructions are unsafe. Sure enough the ARM-ARM makes some
> comments to that extent, but the comments are a bit obtuse
> (to me anyway). It may be that in some situations the code
> is unsafe while in others its ok.

ldm/stm are used just about everywhere for stack saving, block copying etc.

There are two forms of stm: stm(1) and stm(2)
There are three forms of ldm: 1,2,3.

The stm(1) form seems to be generally safe whereas the stm(2) form is only 
safe in certain cases (saving the SYS/user register bank while not in that 
mode). How you determine which you get, perhaps someone else knows...

>
> In an earlier version of your port, tasks ran in supervisor
> mode (in which the store/load multiple instructions would
> be deemed safe). From init.S from the lpc2xxx folder, it
> looks like you leave the processor in SVC mode.
> Is this why you chose this mode?
>
> Any other arguments in favor of SVC vs SYS mode?

One argument against leaving things in SVC mode is that you cannot then do 
SWIs, since SWIs need to switch to SVC mode to execute.

>
> Any comments on the store/load-multiple instructions and
> issues with their use?

STM and LDM provide nice compact data shuffling, but they can push out 
interrupt latency since the whole instruction must finish before the 
interrupt can be serviced. For that reason, some compilers allow for 
controlling the maximum number of registers save/restored by an ldm/stm.