Lpc2000

Hi David,

[ My views on the subject ]

--- David Hawkins <dwh@...> wrote:

> 
> Hey Michael,
> 
> In your port os_cpu_a.S, you use the
> store/load-multiple
> instructions in your context save and restore
> routines, whereas
> in Jean Labrosse's versions he uses individual
> instructions.
> 
> The comment made by Jean in one or more of his app
> notes runs 
> along the lines that in User/System mode the
> store/load-multiple 
> instructions are unsafe. Sure enough the ARM-ARM
> makes some 
> comments to that extent, but the comments are a bit
> obtuse
> (to me anyway). It may be that in some situations
> the code 
> is unsafe while in others its ok.
> 
> In an earlier version of your port, tasks ran in
> supervisor
> mode (in which the store/load multiple instructions
> would
> be deemed safe). From init.S from the lpc2xxx
> folder, it
> looks like you leave the processor in SVC mode.

Totally agree with your concern. Just like you said,
the code is run completely in SVC mode till date in
all my ports. And as someone pointed (and mentioned in
the ARM_ARM document) the LDM(3) \ufffd is unsafe only in
System or User mode \ufffd Which is completely avoided in
my port. And the other failure case is when Rn = R15,
which is not true either.

> Is this why you chose this mode? 

You could say that. But, Nope :)
I did not choose this; but rather I chose not to
switch out of SVC, because it is the default mode &
did not find kernel protection to be all that useful
in a monolithic, tight RTOS like this (same philosophy
applies to all my other architecture uCOS-II ports).
Apart from this, I would use system mode briefly to do
nested interrupts as suggested in the ARM_ARM
document.

The RTOS, foreground tasks \ufffd pretty much all the code
except for the ISRs run in SVC mode; I don\ufffdt see any
good reason to support SWI.

[ I have been in primary kernel development roles for
Linux like virtual space user processes (TLB based
MMU) & protected kernel OS on ARM9, where SWI was very
much useful ]

One thought I always have is, Why not SVC?

> 
> Any other arguments in favor of SVC vs SYS mode?
> 
> Any comments on the store/load-multiple instructions
> and
> issues with their use?

Apart from these, the IRQ handler in normal course
(when a Task sw is not required) preserves just the
registers required by ATPCS & the rest of the context
saving happens only when a task context switch is
needed. Due to this you will see some extra coping
done in the int_ctx_sw portion of the code \ufffd And lot
of caution has be taken to work with ARM-THUMB mixed
mode code.

As such the code is thoroughly tested; the same code
(under common) runs in many different flavors of
ARM7/9s.

[ Please feel free to comment, suggest improvements on
the port ]

Cheers,
-Mike.


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