Lpc2000

hi,

because the SPI does not have a FIFO, it might be a great idea to use
the SSP, which has FIFOs. Switching between master and slave mode is
tricky in SSP but otherwise highly recommended to use the SSP.

Bob

--- In lpc2000@yahoogroups.com, "Mark Butcher" <M_J_Butcher@I...> wrote:
> I found this works quite well:
> SPI interface plus 1 interrupt line from slave to master.
> When the master wants to send data it can and the slave is interrupted 
> by the SPI Rx interrupt.
> When the slave wants to send data it interrupts the master via the 
> interrupt line and waits for the master to collect it.
> The transmission may well need a protocol - for example the length of 
> data followed by the data content.
> The other side sends idles (eg. zeros) when there is no data to be 
> returned (ie. no bidirectional transmission). If it wants, it can then 
> also send data while receiving.
> Generally the SPI on the LPC has to be handled carefully since it has 
> no FIFO and overruns are hard to detect. I think that it is possible 
> to set a pattern in the tx register which is automatically sent 
> (repeated) when nothing else is actively returned, and this can be 
> used (with a slightly more complicated protocol) to cause the master 
> side to wait until the slave is actually ready to receive the data.
> My philiosphy due to these compilications is to keep transmissions as 
> short as possible (max transmission speed) and handle reception in a 
> loop until complete and not handle each byte by individual interrupt 
> (assuming the transmissions are irregular short bursts and not 
> continuous.
> 
> Regards
> 
> Mark Butcher
> www.mjbc.ch