Lpc2000

Hello,

In your opinion, what is the best way to transfer data between 2 LPC 
micros using SPI?

The way I have it now, one is master and other is slave. The slave one 
have 1 pin called DATA_READY. When the slave needs to send data to 
master, it sets DATA_READY high.

Now the problem is that when the master reads data, it also writes 
data at the same time (the way SPI works) How would the slave know 
that the SPI transaction is read, write or both.

Thanks,

Gus

It is "always both".  It's up to your protocol to decide which data 
stream is "don't care" and when.  Only the master can initiate an 
exchange on an SPI bus.

Krys

--- In lpc2000@yahoogroups.com, "Gus" <gus_is_working@y...> wrote:
> Hello,
> 
> In your opinion, what is the best way to transfer data between 2 
LPC 
> micros using SPI?
> 
> The way I have it now, one is master and other is slave. The slave 
one 

> have 1 pin called DATA_READY. When the slave needs to send data to 
> master, it sets DATA_READY high.
> 
> Now the problem is that when the master reads data, it also writes 
> data at the same time (the way SPI works) How would the slave know 
> that the SPI transaction is read, write or both.
> 
> Thanks,
> 
> Gus

I know that! My question is what is the best way to do that protocol.

Gus
--- In lpc2000@yahoogroups.com, "y4krys" <krys.brukalo@a...> wrote:
> It is "always both".  It's up to your protocol to decide which 
data 
> stream is "don't care" and when.  Only the master can initiate an 
> exchange on an SPI bus.
> 
> Krys
> 
> --- In lpc2000@yahoogroups.com, "Gus" <gus_is_working@y...> wrote:
> > Hello,
> > 
> > In your opinion, what is the best way to transfer data between 2 
> LPC 
> > micros using SPI?
> > 
> > The way I have it now, one is master and other is slave. The 
slave 
> one 
> > have 1 pin called DATA_READY. When the slave needs to send data 
to 
> > master, it sets DATA_READY high.
> > 
> > Now the problem is that when the master reads data, it also 
writes 
> > data at the same time (the way SPI works) How would the slave 
know 

> > that the SPI transaction is read, write or both.
> > 
> > Thanks,
> > 
> > Gus

As always, it depends ;-).  Here is what I think:
- first, your slave should listen to be able to receive your master 
command data.  Your master wouldn't care much for the data send from 
the slave until the end of your frame, when an ack from the slave 
would be a good thing to have.
- second, the behaviour of both the master and the slave depends on 
your command.

This is a simple scenario.  Many SPI protocols take full advantage 
from the fact the data can be sent and received at the same time.  
Your slave can, and ususlly shoud, have same data ready for the next 
exchange.  If not, perhaps an asynch bus would be a better choice?

I hope it is helpful.  I'd have to know much more about your project 
to sugest anything more specific.

Krys

--- In lpc2000@yahoogroups.com, "Gus" <gus_is_working@y...> wrote:
> I know that! My question is what is the best way to do that 
protocol.
> 
> Gus
> --- In lpc2000@yahoogroups.com, "y4krys" <krys.brukalo@a...> wrote:
> > It is "always both".  It's up to your protocol to decide which 
> data 
> > stream is "don't care" and when.  Only the master can initiate an 
> > exchange on an SPI bus.
> > 
> > Krys
> > 
> > --- In lpc2000@yahoogroups.com, "Gus" <gus_is_working@y...> wrote:
> > > Hello,
> > > 
> > > In your opinion, what is the best way to transfer data between 
2 

> > LPC 
> > > micros using SPI?
> > > 
> > > The way I have it now, one is master and other is slave. The 
> slave 
> > one 
> > > have 1 pin called DATA_READY. When the slave needs to send data 
> to 
> > > master, it sets DATA_READY high.
> > > 
> > > Now the problem is that when the master reads data, it also 
> writes 
> > > data at the same time (the way SPI works) How would the slave 
> know 
> > > that the SPI transaction is read, write or both.
> > > 
> > > Thanks,
> > > 
> > > Gus

I found this works quite well:
SPI interface plus 1 interrupt line from slave to master.
When the master wants to send data it can and the slave is interrupted 
by the SPI Rx interrupt.
When the slave wants to send data it interrupts the master via the 
interrupt line and waits for the master to collect it.
The transmission may well need a protocol - for example the length of 
data followed by the data content.
The other side sends idles (eg. zeros) when there is no data to be 
returned (ie. no bidirectional transmission). If it wants, it can then 
also send data while receiving.
Generally the SPI on the LPC has to be handled carefully since it has 
no FIFO and overruns are hard to detect. I think that it is possible 
to set a pattern in the tx register which is automatically sent 
(repeated) when nothing else is actively returned, and this can be 
used (with a slightly more complicated protocol) to cause the master 
side to wait until the slave is actually ready to receive the data.
My philiosphy due to these compilications is to keep transmissions as 
short as possible (max transmission speed) and handle reception in a 
loop until complete and not handle each byte by individual interrupt 
(assuming the transmissions are irregular short bursts and not 
continuous.

Regards

Mark Butcher
www.mjbc.ch

hi,

because the SPI does not have a FIFO, it might be a great idea to use
the SSP, which has FIFOs. Switching between master and slave mode is
tricky in SSP but otherwise highly recommended to use the SSP.

Bob

--- In lpc2000@yahoogroups.com, "Mark Butcher" <M_J_Butcher@I...> wrote:

> I found this works quite well:
> SPI interface plus 1 interrupt line from slave to master.
> When the master wants to send data it can and the slave is interrupted 
> by the SPI Rx interrupt.
> When the slave wants to send data it interrupts the master via the 
> interrupt line and waits for the master to collect it.
> The transmission may well need a protocol - for example the length of 
> data followed by the data content.
> The other side sends idles (eg. zeros) when there is no data to be 
> returned (ie. no bidirectional transmission). If it wants, it can then 
> also send data while receiving.
> Generally the SPI on the LPC has to be handled carefully since it has 
> no FIFO and overruns are hard to detect. I think that it is possible 
> to set a pattern in the tx register which is automatically sent 
> (repeated) when nothing else is actively returned, and this can be 
> used (with a slightly more complicated protocol) to cause the master 
> side to wait until the slave is actually ready to receive the data.
> My philiosphy due to these compilications is to keep transmissions as 
> short as possible (max transmission speed) and handle reception in a 
> loop until complete and not handle each byte by individual interrupt 
> (assuming the transmissions are irregular short bursts and not 
> continuous.
> 
> Regards
> 
> Mark Butcher
> www.mjbc.ch

This is almost what I have. I think what I am doing is not wrong 
then :)

thanks to all who answered

Gus
--- In lpc2000@yahoogroups.com, "Mark Butcher" <M_J_Butcher@I...> 
wrote:
> I found this works quite well:
> SPI interface plus 1 interrupt line from slave to master.
> When the master wants to send data it can and the slave is 
interrupted 
> by the SPI Rx interrupt.
> When the slave wants to send data it interrupts the master via the 
> interrupt line and waits for the master to collect it.
> The transmission may well need a protocol - for example the length 
of 
> data followed by the data content.
> The other side sends idles (eg. zeros) when there is no data to be 
> returned (ie. no bidirectional transmission). If it wants, it can 
then 
> also send data while receiving.
> Generally the SPI on the LPC has to be handled carefully since it 
has 
> no FIFO and overruns are hard to detect. I think that it is 
possible 
> to set a pattern in the tx register which is automatically sent 
> (repeated) when nothing else is actively returned, and this can be 
> used (with a slightly more complicated protocol) to cause the 
master 
> side to wait until the slave is actually ready to receive the data.
> My philiosphy due to these compilications is to keep transmissions 
as 
> short as possible (max transmission speed) and handle reception in 
a 
> loop until complete and not handle each byte by individual 
interrupt 

> (assuming the transmissions are irregular short bursts and not 
> continuous.
> 
> Regards
> 
> Mark Butcher
> www.mjbc.ch