Lpc2000

Karl Olsen wrote:

>
>For example, LDR with R15 destination (such as LDR PC, [R0, #0]) is 
>listed as "+N +I +N +2S", which for the LPC2xxx means 1+1+1+2 = 5 
>clocks.  Assuming that R0 points to RAM and the word loaded from 
>there points to somewhere in flash, add 0 for the RAM load (RAM is 
>always 0 waitstates), and 2 for the initial nonsequential code fetch 
>from flash (with MAMTIM=3), giving a total of 7 clocks.
>
>For newer ARM cores, such as the ARM920 with caches and multiple 
>pipeline stages after decode, it is a different story.
>
>  
>

Thank you, I did not realize that the TDMI core differed that much from 
the regular core.

TomW

-- 
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net, http://cyberiansoftware.com
"Windows? No thanks, I have work to do..."
----------------------------------------------------