Lpc2000

Thanks, Sten. In fact, I was reading the errata when all these 
questions came to my mind. :)
I think I got it now.

Guille

--- In lpc2000@yahoogroups.com, Sten <list@n...> wrote:
>
> Hello Guille,
> 
> In generall you can't miss an interrupt because interrupt flags can 
only
> be reseted if the interrupt condition has been satisfied. If you 
still
> have received bytes in your receive hold register or your transmit 
hold
> register is still empty the interrupt will occur again and again 
until
> it is turned off or received data read or transmit register feed. 
But
> you should read the errata before, because some interrupt stuff is 
not
> working correctly! ;-)
> If your interrupt has not been satisfied or another interrupt is 
pending
> a new exeption will occur immediately after your return from 
interrupt.
> Be carefully: you DO NOT have to restore CSPR manually on ARM
> achitecture. ARM7 has six different operating modes with independent
> register sets! If an interrupt is executed the ARM architecture 
enters a
> seraprate mode (IRQ or FIQ mode for "normal" interrupts). Some 
registers
> (incl. CPSR, LR, SP) are hold in a shadow register of your previous
> mode. If you return from interrupt the old content is restored by
> hardware. So DON'T TOUCH CPSR[IRQ|FIQ] inside an interrupt service
> routine! If you re-enable IRQ&FIQ in your interrupt service 
routine, the
> next pending interrupt my be executed before you can return from 
this
> interrupt. This might not what you expect! This technique is called
> "nested interrupts" which implementation is a little bit tricky 
with ARM
> architectures due to the content switch of operating modes. This is
> totaly different to other architectures.
> See ARM7TDMI reference manual chapter 2.6ff.
> 
> Regards,
>    Sten
> 
> Guillermo Prandi wrote:
> > Thanks, Richard.
> > 
> > So, if I understand correctly, if I don't clear the interrupts in 
my 
> > interrupt handler (or a new interrupt happens while at the 
handler) 
> > the handler will be called again as soon as I restore the CSPR 
> > register, which should happen at my final MOVS PC,LR?
> > 
> > I'm worried about inadvertently writing code that would miss 
> > interrupts. As I get from your explanation, that's easy to avoid.
> > 
> > Guille
> > 
> 
> 
> -- 
> /************************************************
>  Do you need a tiny and efficient real time
>  operating system (RTOS) with a preemtive
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> 
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> 
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> 
>    http://www.net-attack.de/
> 
> ************************************************/
>