Lpc2000

Hi! I read every doc I've found and I couldn't get a detailed 
description of the interrupt mechanism in the LPC2XXX. In particular, 
I'm looking for the following:

- What happens to interrupts while they're disabled? Do they 
get "cached"? I mean, if I'm in the middle of processing a UART0 
interrupt and UART1 receives a new character, I'd probably have the 
interrupts disabled. Will I miss the interrupt?

- Provided the interrupts get chached while disabled somehow... That 
would mean that they will trigger as soon as they're enabled, isn't it? 
I plan to keep interrupts disabled while processing other interrupts; 
could that work?

- What's the exact difference between edge and level triggered 
interrupts?

Thanks in advance

With everything that generates an interrupt, you have to clear the 
interrupt by reading or writing to a register. For example with the UART 
you clear a data ready interrupt by reading the data. If you cannot 
clear the interrupt (for example a UART transmit holding register emty 
while you have nothing to send), you disable it. If you do not clear or 
disable the interrupt, the interrupt will be called again immidiately 
after you return from it.

Level sensitive interrupts are active if the input pin is low (high if 
INTPOLAR bit is set), edge sensitive interrupts become active on the 
high to low transition (if INTPOLAR bit is clear) of the input pin. All 
internal interrupts are level sensitive. External interrupts are cached 
and converted to level senstive interrupt by the external interrupt 
controller.



Guillermo Prandi wrote:

> Hi! I read every doc I've found and I couldn't get a detailed
> description of the interrupt mechanism in the LPC2XXX. In particular,
> I'm looking for the following:
>
> - What happens to interrupts while they're disabled? Do they
> get "cached"? I mean, if I'm in the middle of processing a UART0
> interrupt and UART1 receives a new character, I'd probably have the
> interrupts disabled. Will I miss the interrupt?
>
> - Provided the interrupts get chached while disabled somehow... That
> would mean that they will trigger as soon as they're enabled, isn't it?
> I plan to keep interrupts disabled while processing other interrupts;
> could that work?
>
> - What's the exact difference between edge and level triggered
> interrupts?
>
> Thanks in advance
>
>
>
>
>
> SPONSORED LINKS
> Microprocessor 
> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
> 	Microcontrollers 
> <http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg> 
> 	Pic microcontrollers 
> <http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ> 
>
> 8051 microprocessor 
> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
>
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Thanks, Richard.

So, if I understand correctly, if I don't clear the interrupts in my 
interrupt handler (or a new interrupt happens while at the handler) 
the handler will be called again as soon as I restore the CSPR 
register, which should happen at my final MOVS PC,LR?

I'm worried about inadvertently writing code that would miss 
interrupts. As I get from your explanation, that's easy to avoid.

Guille

--- In lpc2000@yahoogroups.com, Richard Duits <yahoo@r...> wrote:
>
> With everything that generates an interrupt, you have to clear the 
> interrupt by reading or writing to a register. For example with the 
UART 
> you clear a data ready interrupt by reading the data. If you cannot 
> clear the interrupt (for example a UART transmit holding register 
emty 
> while you have nothing to send), you disable it. If you do not 
clear or 
> disable the interrupt, the interrupt will be called again 
immidiately 
> after you return from it.
> 
> Level sensitive interrupts are active if the input pin is low (high 
if 
> INTPOLAR bit is set), edge sensitive interrupts become active on 
the 
> high to low transition (if INTPOLAR bit is clear) of the input pin. 
All 
> internal interrupts are level sensitive. External interrupts are 
cached 
> and converted to level senstive interrupt by the external interrupt 
> controller.
> 
> 
> 
> Guillermo Prandi wrote:
> 
> > Hi! I read every doc I've found and I couldn't get a detailed
> > description of the interrupt mechanism in the LPC2XXX. In 
particular,
> > I'm looking for the following:
> >
> > - What happens to interrupts while they're disabled? Do they
> > get "cached"? I mean, if I'm in the middle of processing a UART0
> > interrupt and UART1 receives a new character, I'd probably have 
the
> > interrupts disabled. Will I miss the interrupt?
> >
> > - Provided the interrupts get chached while disabled somehow... 
That
> > would mean that they will trigger as soon as they're enabled, 
isn't it?
> > I plan to keep interrupts disabled while processing other 
interrupts;
> > could that work?
> >
> > - What's the exact difference between edge and level triggered
> > interrupts?
> >
> > Thanks in advance
> >
> >
> >
> >
> >
> > SPONSORED LINKS
> > Microprocessor 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
J9hJ5qyXg0WPR0l6g> 
> > 	Microcontrollers 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
1nxwg> 
> > 	Pic microcontrollers 
> > <http://groups.yahoo.com/gads?
t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
6LyBvUqVQ> 
> >
> > 8051 microprocessor 
> > <http://groups.yahoo.com/gads?
t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
lekkDP-A> 
> >
> >
> >
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------
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Hello Guille,

In generall you can't miss an interrupt because interrupt flags can only
be reseted if the interrupt condition has been satisfied. If you still
have received bytes in your receive hold register or your transmit hold
register is still empty the interrupt will occur again and again until
it is turned off or received data read or transmit register feed. But
you should read the errata before, because some interrupt stuff is not
working correctly! ;-)
If your interrupt has not been satisfied or another interrupt is pending
a new exeption will occur immediately after your return from interrupt.
Be carefully: you DO NOT have to restore CSPR manually on ARM
achitecture. ARM7 has six different operating modes with independent
register sets! If an interrupt is executed the ARM architecture enters a
seraprate mode (IRQ or FIQ mode for "normal" interrupts). Some registers
(incl. CPSR, LR, SP) are hold in a shadow register of your previous
mode. If you return from interrupt the old content is restored by
hardware. So DON'T TOUCH CPSR[IRQ|FIQ] inside an interrupt service
routine! If you re-enable IRQ&FIQ in your interrupt service routine, the
next pending interrupt my be executed before you can return from this
interrupt. This might not what you expect! This technique is called
"nested interrupts" which implementation is a little bit tricky with ARM
architectures due to the content switch of operating modes. This is
totaly different to other architectures.
See ARM7TDMI reference manual chapter 2.6ff.

Regards,
   Sten

Guillermo Prandi wrote:
> Thanks, Richard.
> 
> So, if I understand correctly, if I don't clear the interrupts in my 
> interrupt handler (or a new interrupt happens while at the handler) 
> the handler will be called again as soon as I restore the CSPR 
> register, which should happen at my final MOVS PC,LR?
> 
> I'm worried about inadvertently writing code that would miss 
> interrupts. As I get from your explanation, that's easy to avoid.
> 
> Guille
> 


-- 
/************************************************
 Do you need a tiny and efficient real time
 operating system (RTOS) with a preemtive
 multitasking for LPC2000 or AT91SAM7?

   http://nanortos.net-attack.de/

 Or some open-source tools and code for LPC2000?

   http://www.net-attack.de/

************************************************/

Thanks, Sten. In fact, I was reading the errata when all these 
questions came to my mind. :)
I think I got it now.

Guille

--- In lpc2000@yahoogroups.com, Sten <list@n...> wrote:
>
> Hello Guille,
> 
> In generall you can't miss an interrupt because interrupt flags can 
only
> be reseted if the interrupt condition has been satisfied. If you 
still
> have received bytes in your receive hold register or your transmit 
hold
> register is still empty the interrupt will occur again and again 
until
> it is turned off or received data read or transmit register feed. 
But
> you should read the errata before, because some interrupt stuff is 
not
> working correctly! ;-)
> If your interrupt has not been satisfied or another interrupt is 
pending
> a new exeption will occur immediately after your return from 
interrupt.
> Be carefully: you DO NOT have to restore CSPR manually on ARM
> achitecture. ARM7 has six different operating modes with independent
> register sets! If an interrupt is executed the ARM architecture 
enters a
> seraprate mode (IRQ or FIQ mode for "normal" interrupts). Some 
registers
> (incl. CPSR, LR, SP) are hold in a shadow register of your previous
> mode. If you return from interrupt the old content is restored by
> hardware. So DON'T TOUCH CPSR[IRQ|FIQ] inside an interrupt service
> routine! If you re-enable IRQ&FIQ in your interrupt service 
routine, the
> next pending interrupt my be executed before you can return from 
this
> interrupt. This might not what you expect! This technique is called
> "nested interrupts" which implementation is a little bit tricky 
with ARM
> architectures due to the content switch of operating modes. This is
> totaly different to other architectures.
> See ARM7TDMI reference manual chapter 2.6ff.
> 
> Regards,
>    Sten
> 
> Guillermo Prandi wrote:
> > Thanks, Richard.
> > 
> > So, if I understand correctly, if I don't clear the interrupts in 
my 
> > interrupt handler (or a new interrupt happens while at the 
handler) 

> > the handler will be called again as soon as I restore the CSPR 
> > register, which should happen at my final MOVS PC,LR?
> > 
> > I'm worried about inadvertently writing code that would miss 
> > interrupts. As I get from your explanation, that's easy to avoid.
> > 
> > Guille
> > 
> 
> 
> -- 
> /************************************************
>  Do you need a tiny and efficient real time
>  operating system (RTOS) with a preemtive
>  multitasking for LPC2000 or AT91SAM7?
> 
>    http://nanortos.net-attack.de/
> 
>  Or some open-source tools and code for LPC2000?
> 
>    http://www.net-attack.de/
> 
> ************************************************/
>

It's almost impossible to miss an interrupt. Your only worry is that you 
respond to the interrupt in time. For example the UART can only buffer a 
number of bytes (16 if you use the fifo). If you respond to the UART 
receive interrupt to late, you get an overrun and data is lost. So you 
cannot miss an interrupt, but be carefull that you do not write to much 
code in the interupt handlers. Very long interrupt handlers can delay 
another interrupt so long that something may go wrong. This is called a 
deadline.

Richard Duits



Guillermo Prandi wrote:

> Thanks, Richard.
>
> So, if I understand correctly, if I don't clear the interrupts in my
> interrupt handler (or a new interrupt happens while at the handler)
> the handler will be called again as soon as I restore the CSPR
> register, which should happen at my final MOVS PC,LR?
>
> I'm worried about inadvertently writing code that would miss
> interrupts. As I get from your explanation, that's easy to avoid.
>
> Guille
>
> --- In lpc2000@yahoogroups.com, Richard Duits <yahoo@r...> wrote:
> >
> > With everything that generates an interrupt, you have to clear the
> > interrupt by reading or writing to a register. For example with the
> UART
> > you clear a data ready interrupt by reading the data. If you cannot
> > clear the interrupt (for example a UART transmit holding register
> emty
> > while you have nothing to send), you disable it. If you do not
> clear or
> > disable the interrupt, the interrupt will be called again
> immidiately
> > after you return from it.
> >
> > Level sensitive interrupts are active if the input pin is low (high
> if
> > INTPOLAR bit is set), edge sensitive interrupts become active on
> the
> > high to low transition (if INTPOLAR bit is clear) of the input pin.
> All
> > internal interrupts are level sensitive. External interrupts are
> cached
> > and converted to level senstive interrupt by the external interrupt
> > controller.
> >
> >
> >
> > Guillermo Prandi wrote:
> >
> > > Hi! I read every doc I've found and I couldn't get a detailed
> > > description of the interrupt mechanism in the LPC2XXX. In
> particular,
> > > I'm looking for the following:
> > >
> > > - What happens to interrupts while they're disabled? Do they
> > > get "cached"? I mean, if I'm in the middle of processing a UART0
> > > interrupt and UART1 receives a new character, I'd probably have
> the
> > > interrupts disabled. Will I miss the interrupt?
> > >
> > > - Provided the interrupts get chached while disabled somehow...
> That
> > > would mean that they will trigger as soon as they're enabled,
> isn't it?
> > > I plan to keep interrupts disabled while processing other
> interrupts;
> > > could that work?
> > >
> > > - What's the exact difference between edge and level triggered
> > > interrupts?
> > >
> > > Thanks in advance
> > >
> > >
> > >
> > >
> > >
> > > SPONSORED LINKS
> > > Microprocessor
> > > <http://groups.yahoo.com/gads?
> t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
> rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
> J9hJ5qyXg0WPR0l6g>
> > >       Microcontrollers
> > > <http://groups.yahoo.com/gads?
> t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
> icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
> 1nxwg>
> > >       Pic microcontrollers
> > > <http://groups.yahoo.com/gads?
> t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
> ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
> 6LyBvUqVQ>
> > >
> > > 8051 microprocessor
> > > <http://groups.yahoo.com/gads?
> t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
> c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
> lekkDP-A>
> > >
> > >
> > >
> > > ------------------------------------------------------------------
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> > >
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> subject=Unsubscribe>
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> > >     *  Your use of Yahoo! Groups is subject to the Yahoo! Terms of
> > >       Service <http://docs.yahoo.com/info/terms/>.
> > >
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> > > ------------------------------------------------------------------
> ------
> > >
> >
>
>
>
>
>
>
> SPONSORED LINKS
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> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
> 	Microcontrollers 
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> 	Pic microcontrollers 
> <http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ> 
>
> 8051 microprocessor 
> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
>
>
>
> ------------------------------------------------------------------------
> YAHOO! GROUPS LINKS
>
>     *  Visit your group "lpc2000
>       <http://groups.yahoo.com/group/lpc2000>" on the web.
>        
>     *  To unsubscribe from this group, send an email to:
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>
> ------------------------------------------------------------------------
>

Good advice, Richard. I'll take it. Thanks.

--- In lpc2000@yahoogroups.com, Richard Duits <yahoo@r...> wrote:
>
> It's almost impossible to miss an interrupt. Your only worry is 
that you 
> respond to the interrupt in time. For example the UART can only 
buffer a 
> number of bytes (16 if you use the fifo). If you respond to the 
UART 
> receive interrupt to late, you get an overrun and data is lost. So 
you 
> cannot miss an interrupt, but be carefull that you do not write to 
much 
> code in the interupt handlers. Very long interrupt handlers can 
delay 
> another interrupt so long that something may go wrong. This is 
called a 
> deadline.
> 
> Richard Duits
> 
> 
> 
> Guillermo Prandi wrote:
> 
> > Thanks, Richard.
> >
> > So, if I understand correctly, if I don't clear the interrupts in 
my
> > interrupt handler (or a new interrupt happens while at the 
handler)
> > the handler will be called again as soon as I restore the CSPR
> > register, which should happen at my final MOVS PC,LR?
> >
> > I'm worried about inadvertently writing code that would miss
> > interrupts. As I get from your explanation, that's easy to avoid.
> >
> > Guille
> >
> > --- In lpc2000@yahoogroups.com, Richard Duits <yahoo@r...> wrote:
> > >
> > > With everything that generates an interrupt, you have to clear 
the
> > > interrupt by reading or writing to a register. For example with 
the
> > UART
> > > you clear a data ready interrupt by reading the data. If you 
cannot
> > > clear the interrupt (for example a UART transmit holding 
register
> > emty
> > > while you have nothing to send), you disable it. If you do not
> > clear or
> > > disable the interrupt, the interrupt will be called again
> > immidiately
> > > after you return from it.
> > >
> > > Level sensitive interrupts are active if the input pin is low 
(high
> > if
> > > INTPOLAR bit is set), edge sensitive interrupts become active on
> > the
> > > high to low transition (if INTPOLAR bit is clear) of the input 
pin.
> > All
> > > internal interrupts are level sensitive. External interrupts are
> > cached
> > > and converted to level senstive interrupt by the external 
interrupt
> > > controller.
> > >
> > >
> > >
> > > Guillermo Prandi wrote:
> > >
> > > > Hi! I read every doc I've found and I couldn't get a detailed
> > > > description of the interrupt mechanism in the LPC2XXX. In
> > particular,
> > > > I'm looking for the following:
> > > >
> > > > - What happens to interrupts while they're disabled? Do they
> > > > get "cached"? I mean, if I'm in the middle of processing a 
UART0
> > > > interrupt and UART1 receives a new character, I'd probably 
have
> > the
> > > > interrupts disabled. Will I miss the interrupt?
> > > >
> > > > - Provided the interrupts get chached while disabled 
somehow...
> > That
> > > > would mean that they will trigger as soon as they're enabled,
> > isn't it?
> > > > I plan to keep interrupts disabled while processing other
> > interrupts;
> > > > could that work?
> > > >
> > > > - What's the exact difference between edge and level triggered
> > > > interrupts?
> > > >
> > > > Thanks in advance
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > SPONSORED LINKS
> > > > Microprocessor
> > > > <http://groups.yahoo.com/gads?
> > 
t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
> > rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
> > J9hJ5qyXg0WPR0l6g>
> > > >       Microcontrollers
> > > > <http://groups.yahoo.com/gads?
> > 
t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
> > 
icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
> > 1nxwg>
> > > >       Pic microcontrollers
> > > > <http://groups.yahoo.com/gads?
> > 
t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
> > 
ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
> > 6LyBvUqVQ>
> > > >
> > > > 8051 microprocessor
> > > > <http://groups.yahoo.com/gads?
> > 
t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
> > 
c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
> > lekkDP-A>
> > > >
> > > >
> > > >
> > > > --------------------------------------------------------------
----
> > ------
> > > > YAHOO! GROUPS LINKS
> > > >
> > > >     *  Visit your group "lpc2000
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> > > >       
> > > >     *  To unsubscribe from this group, send an email to:
> > > >        lpc2000-unsubscribe@yahoogroups.com
> > > >       <mailto:lpc2000-unsubscribe@yahoogroups.com?
> > subject=Unsubscribe>
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> > > >     *  Your use of Yahoo! Groups is subject to the Yahoo! 
Terms of
> > > >       Service <http://docs.yahoo.com/info/terms/>.
> > > >
> > > >
> > > > --------------------------------------------------------------
----
> > ------
> > > >
> > >
> >
> >
> >
> >
> >
> >
> > SPONSORED LINKS
> > Microprocessor 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
J9hJ5qyXg0WPR0l6g> 
> > 	Microcontrollers 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
1nxwg> 
> > 	Pic microcontrollers 
> > <http://groups.yahoo.com/gads?
t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
6LyBvUqVQ> 
> >
> > 8051 microprocessor 
> > <http://groups.yahoo.com/gads?
t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
lekkDP-A> 
> >
> >
> >
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