Lpc2000

Long time lurker, first time poster...

I've set the SPIE bit in the Control Register.  I can see the SPIF bit
get set in the Status Register.  However, I do NOT see the SPI
Interrupt bit get set in the Interrupt Register.  Shouldn't this occur
as soon as the SPIF bit is set, regardless of how the VIC is set up? 
I have the VIC set up "correctly", but the ISR never executes
(presumably because the SPI Interrupt never fires).  I've had
interrupts working correctly for UART0 and a timer, so I know that
interrupts can work (they just aren't in this occasion).

I can do non-interrupt SPI transmits (i.e. the 1st byte of an
interrupt-based multibye transfer) so I know the hardware is ok (SSEL
= 1).  I've duplicated this on the MCB2130 and a LPC2214 dev board.

Any insight from those that have implemented interrupt based SPI is
appreciated.

Stumped in Seattle...

ee_gary wrote:
> Long time lurker, first time poster...
> 
> I've set the SPIE bit in the Control Register.  I can see the SPIF bit
> get set in the Status Register.  However, I do NOT see the SPI
> Interrupt bit get set in the Interrupt Register.  Shouldn't this occur
> as soon as the SPIF bit is set, regardless of how the VIC is set up? 
> I have the VIC set up "correctly", but the ISR never executes
> (presumably because the SPI Interrupt never fires).  I've had
> interrupts working correctly for UART0 and a timer, so I know that
> interrupts can work (they just aren't in this occasion).
> 
> I can do non-interrupt SPI transmits (i.e. the 1st byte of an
> interrupt-based multibye transfer) so I know the hardware is ok (SSEL
> = 1).  I've duplicated this on the MCB2130 and a LPC2214 dev board.
> 
> Any insight from those that have implemented interrupt based SPI is
> appreciated.
> 
> Stumped in Seattle...
> 

Please can you send a small portion of source code? It sounds unbelievable.

  Sten

-- 
/************************************************
 Do you need a tiny and efficient real time
 operating system (RTOS) with a preemtive
 multitasking for LPC2000 or AT91SAM7?

   http://nanortos.net-attack.de/

 Or some open-source tools and code for LPC2000?

   http://www.net-attack.de/

************************************************/

--- In lpc2000@yahoogroups.com, Sten <list@n...> wrote:
>
> ee_gary wrote:
> > Long time lurker, first time poster...
> > 
> > I've set the SPIE bit in the Control Register.  I can see the SPIF bit
> > get set in the Status Register.  However, I do NOT see the SPI
> > Interrupt bit get set in the Interrupt Register.  Shouldn't this occur
> > as soon as the SPIF bit is set, regardless of how the VIC is set up? 
> > I have the VIC set up "correctly", but the ISR never executes
> > (presumably because the SPI Interrupt never fires).  I've had
> > interrupts working correctly for UART0 and a timer, so I know that
> > interrupts can work (they just aren't in this occasion).
> > 
> > I can do non-interrupt SPI transmits (i.e. the 1st byte of an
> > interrupt-based multibye transfer) so I know the hardware is ok (SSEL
> > = 1).  I've duplicated this on the MCB2130 and a LPC2214 dev board.
> > 
> > Any insight from those that have implemented interrupt based SPI is
> > appreciated.
> > 
> > Stumped in Seattle...
> > 
> 
> Please can you send a small portion of source code? It sounds
unbelievable.
> 
>   Sten
> 
> -- 
> /************************************************
>  Do you need a tiny and efficient real time
>  operating system (RTOS) with a preemtive
>  multitasking for LPC2000 or AT91SAM7?
> 
>    http://nanortos.net-attack.de/
> 
>  Or some open-source tools and code for LPC2000?
> 
>    http://www.net-attack.de/
> 
> ************************************************/
>

It'd be my pleasure.  Here's the init function:
void spi0Init(void)
{
  // Set port pins for SPI0
  PINSEL0 = (PINSEL0 & ~S0_PINMASK) | S0_PINSEL;

  // Set SPI Registers
  S0SPCR = 0;           // Clear all bits
  S0SPCR |= SPCR_CPHA;  // Data sampled on rising edge
  S0SPCR |= SPCR_CPOL;	// SCK active low
  S0SPCR |= SPCR_MSTR;	// Master mode

  S0SPSR;         // Cleared by a read of this register
  S0SPDR;         // Cleared by a read of this register
  S0SPCCR = 128;  // 8 is max speed
  S0SPINT = 1;    // Cleared by writing a 1 to it

  // initialize the interrupt vector
  VICIntSelect = 0;  // Select IRQ
  VICIntEnable = 0x00000400;
  VICVectAddr0 = (unsigned long)spi0ISR;
  VICVectCntl0 = 0x0000002A;
									
  // initialize the transmit data queue
  spi0_tx_extract_idx = spi0_tx_insert_idx = 0;
  spi0_tx_running = 0;
}

and the transmit function:
int spi0Putch(int ch)
{
  uint16_t temp;
  unsigned cpsr;

  temp = (spi0_tx_insert_idx + 1) % SPI0_TX_BUFFER_SIZE;

  if (temp == spi0_tx_extract_idx)
    return -1;                          // no room

  cpsr = disableIRQ();                  // disable global interrupts
  S0SPCR &= ~SPCR_SPIE;                 // disable TX interrupts
  restoreIRQ(cpsr);                     // restore global interrupts

  // check if in process of sending data
  if (spi0_tx_running){
    // add to queue
    spi0_tx_buffer[spi0_tx_insert_idx] = (uint8_t)ch;
    spi0_tx_insert_idx = temp;
  }
  else{
    // set running flag and write to output register    
    spi0_tx_running = 1;
    S0SPDR = (uint8_t)ch;
  }
  cpsr = disableIRQ();                  // disable global interrupts
  S0SPCR |= SPCR_SPIE;                  // enable TX interrupts
  restoreIRQ(cpsr);                     // restore global interrupts

  return (uint8_t)ch;
}

and finally, the ISR that never fires...
void spi0ISR(void)
{
  // perform proper ISR entry so thumb-interwork works properly
  ISR_ENTRY();

  // check if more data to send
  if (spi0_tx_insert_idx != spi0_tx_extract_idx){
    S0SPDR = spi0_tx_buffer[spi0_tx_extract_idx++];
    spi0_tx_extract_idx %= SPI0_TX_BUFFER_SIZE;
  }
  else{ // No more to transmit
    S0SPCR &= ~SPCR_SPIE;
    spi0_tx_running = 0;
  }
  
  S0SPINT = 1;  
  VICVectAddr = 0x00000000;   

  ISR_EXIT();
}

It seems like it should be something simple.  Everything looks okay,
but the ISR never fires.

Thanks,

Gary

This is from the LPC2106 errata sheet:

         SPI.1Unintentional clearing of SPI interrupt flagIntroduction:
The SPI interrupt flag is set by the SPI interface to generate an interrupt. It is cleared by writing a 1 to this bit.
         Problem:A write to any register associated with the SPI peripheral will clear the SPI interrupt register.
         work-around:Avoid writing to SPI registers while transmissions are in progress or while SPI interrupts are pending

I believe you Gary.  I had the same problem.  I have been using the 
MCB2130 (2138) and LPC2131 (my hardware).  I finally gave up on the 
SPI interrupt and now just use polling.  Not very efficient, but in 
my application it is acceptable.
Strange thing to me was the fact that it is just the SPI interrupt 
that has caused problems.  I have been able to configure and use 
every other interrupt available, no problem.

-Dave


--- In lpc2000@yahoogroups.com, "ee_gary" <ee_gary@y...> wrote:
>
> --- In lpc2000@...m, Sten <list@n...> wrote:
> >
> > ee_gary wrote:
> > > Long time lurker, first time poster...
> > > 
> > > I've set the SPIE bit in the Control Register.  I can see the 
SPIF bit
> > > get set in the Status Register.  However, I do NOT see the SPI
> > > Interrupt bit get set in the Interrupt Register.  Shouldn't 
this occur
> > > as soon as the SPIF bit is set, regardless of how the VIC is 
set up? 
> > > I have the VIC set up "correctly", but the ISR never executes
> > > (presumably because the SPI Interrupt never fires).  I've had
> > > interrupts working correctly for UART0 and a timer, so I know 
that
> > > interrupts can work (they just aren't in this occasion).
> > > 
> > > I can do non-interrupt SPI transmits (i.e. the 1st byte of an
> > > interrupt-based multibye transfer) so I know the hardware is ok 
(SSEL
> > > = 1).  I've duplicated this on the MCB2130 and a LPC2214 dev 
board.
> > > 
> > > Any insight from those that have implemented interrupt based 
SPI is

> > > appreciated.
> > > 
> > > Stumped in Seattle...
> > > 
> > 
> > Please can you send a small portion of source code? It sounds
> unbelievable.
> > 
> >   Sten
> > 
> > -- 
> > /************************************************
> >  Do you need a tiny and efficient real time
> >  operating system (RTOS) with a preemtive
> >  multitasking for LPC2000 or AT91SAM7?
> > 
> >    http://nanortos.net-attack.de/
> > 
> >  Or some open-source tools and code for LPC2000?
> > 
> >    http://www.net-attack.de/
> > 
> > ************************************************/
> >
> 
> It'd be my pleasure.  Here's the init function:
> void spi0Init(void)
> {
>   // Set port pins for SPI0
>   PINSEL0 = (PINSEL0 & ~S0_PINMASK) | S0_PINSEL;
> 
>   // Set SPI Registers
>   S0SPCR = 0;           // Clear all bits
>   S0SPCR |= SPCR_CPHA;  // Data sampled on rising edge
>   S0SPCR |= SPCR_CPOL;	// SCK active low
>   S0SPCR |= SPCR_MSTR;	// Master mode
> 
>   S0SPSR;         // Cleared by a read of this register
>   S0SPDR;         // Cleared by a read of this register
>   S0SPCCR = 128;  // 8 is max speed
>   S0SPINT = 1;    // Cleared by writing a 1 to it
> 
>   // initialize the interrupt vector
>   VICIntSelect = 0;  // Select IRQ
>   VICIntEnable = 0x00000400;
>   VICVectAddr0 = (unsigned long)spi0ISR;
>   VICVectCntl0 = 0x0000002A;
> 								
	
>   // initialize the transmit data queue
>   spi0_tx_extract_idx = spi0_tx_insert_idx = 0;
>   spi0_tx_running = 0;
> }
> 
> and the transmit function:
> int spi0Putch(int ch)
> {
>   uint16_t temp;
>   unsigned cpsr;
> 
>   temp = (spi0_tx_insert_idx + 1) % SPI0_TX_BUFFER_SIZE;
> 
>   if (temp == spi0_tx_extract_idx)
>     return -1;                          // no room
> 
>   cpsr = disableIRQ();                  // disable global interrupts
>   S0SPCR &= ~SPCR_SPIE;                 // disable TX interrupts
>   restoreIRQ(cpsr);                     // restore global interrupts
> 
>   // check if in process of sending data
>   if (spi0_tx_running){
>     // add to queue
>     spi0_tx_buffer[spi0_tx_insert_idx] = (uint8_t)ch;
>     spi0_tx_insert_idx = temp;
>   }
>   else{
>     // set running flag and write to output register    
>     spi0_tx_running = 1;
>     S0SPDR = (uint8_t)ch;
>   }
>   cpsr = disableIRQ();                  // disable global interrupts
>   S0SPCR |= SPCR_SPIE;                  // enable TX interrupts
>   restoreIRQ(cpsr);                     // restore global interrupts
> 
>   return (uint8_t)ch;
> }
> 
> and finally, the ISR that never fires...
> void spi0ISR(void)
> {
>   // perform proper ISR entry so thumb-interwork works properly
>   ISR_ENTRY();
> 
>   // check if more data to send
>   if (spi0_tx_insert_idx != spi0_tx_extract_idx){
>     S0SPDR = spi0_tx_buffer[spi0_tx_extract_idx++];
>     spi0_tx_extract_idx %= SPI0_TX_BUFFER_SIZE;
>   }
>   else{ // No more to transmit
>     S0SPCR &= ~SPCR_SPIE;
>     spi0_tx_running = 0;
>   }
>   
>   S0SPINT = 1;  
>   VICVectAddr = 0x00000000;   
> 
>   ISR_EXIT();
> }
> 
> It seems like it should be something simple.  Everything looks okay,
> but the ISR never fires.
> 
> Thanks,
> 
> Gary
>

Same experience here. Tried to do the interrupt thing, now I just start 
the SPI transfer, do some other stuff and then poll until the transfer 
is ready. Is there anybody that has used the SPI interrupt successfully???

Richard Duits.


drb5599 wrote:

> I believe you Gary.  I had the same problem.  I have been using the
> MCB2130 (2138) and LPC2131 (my hardware).  I finally gave up on the
> SPI interrupt and now just use polling.  Not very efficient, but in
> my application it is acceptable.
> Strange thing to me was the fact that it is just the SPI interrupt
> that has caused problems.  I have been able to configure and use
> every other interrupt available, no problem.
>
> -Dave
>
>
> --- In lpc2000@yahoogroups.com, "ee_gary" <ee_gary@y...> wrote:
> >
> > --- In lpc2000@yahoogroups.com, Sten <list@n...> wrote:
> > >
> > > ee_gary wrote:
> > > > Long time lurker, first time poster...
> > > >
> > > > I've set the SPIE bit in the Control Register.  I can see the
> SPIF bit
> > > > get set in the Status Register.  However, I do NOT see the SPI
> > > > Interrupt bit get set in the Interrupt Register.  Shouldn't
> this occur
> > > > as soon as the SPIF bit is set, regardless of how the VIC is
> set up?
> > > > I have the VIC set up "correctly", but the ISR never executes
> > > > (presumably because the SPI Interrupt never fires).  I've had
> > > > interrupts working correctly for UART0 and a timer, so I know
> that
> > > > interrupts can work (they just aren't in this occasion).
> > > >
> > > > I can do non-interrupt SPI transmits (i.e. the 1st byte of an
> > > > interrupt-based multibye transfer) so I know the hardware is ok
> (SSEL
> > > > = 1).  I've duplicated this on the MCB2130 and a LPC2214 dev
> board.
> > > >
> > > > Any insight from those that have implemented interrupt based
> SPI is
> > > > appreciated.
> > > >
> > > > Stumped in Seattle...
> > > >
> > >
> > > Please can you send a small portion of source code? It sounds
> > unbelievable.
> > >
> > >   Sten
> > >
> > > --
> > > /************************************************
> > >  Do you need a tiny and efficient real time
> > >  operating system (RTOS) with a preemtive
> > >  multitasking for LPC2000 or AT91SAM7?
> > >
> > >    http://nanortos.net-attack.de/
> > >
> > >  Or some open-source tools and code for LPC2000?
> > >
> > >    http://www.net-attack.de/
> > >
> > > ************************************************/
> > >
> >
> > It'd be my pleasure.  Here's the init function:
> > void spi0Init(void)
> > {
> >   // Set port pins for SPI0
> >   PINSEL0 = (PINSEL0 & ~S0_PINMASK) | S0_PINSEL;
> >
> >   // Set SPI Registers
> >   S0SPCR = 0;           // Clear all bits
> >   S0SPCR |= SPCR_CPHA;  // Data sampled on rising edge
> >   S0SPCR |= SPCR_CPOL;      // SCK active low
> >   S0SPCR |= SPCR_MSTR;      // Master mode
> >
> >   S0SPSR;         // Cleared by a read of this register
> >   S0SPDR;         // Cleared by a read of this register
> >   S0SPCCR = 128;  // 8 is max speed
> >   S0SPINT = 1;    // Cleared by writing a 1 to it
> >
> >   // initialize the interrupt vector
> >   VICIntSelect = 0;  // Select IRQ
> >   VICIntEnable = 0x00000400;
> >   VICVectAddr0 = (unsigned long)spi0ISR;
> >   VICVectCntl0 = 0x0000002A;
> >                                                
>      
> >   // initialize the transmit data queue
> >   spi0_tx_extract_idx = spi0_tx_insert_idx = 0;
> >   spi0_tx_running = 0;
> > }
> >
> > and the transmit function:
> > int spi0Putch(int ch)
> > {
> >   uint16_t temp;
> >   unsigned cpsr;
> >
> >   temp = (spi0_tx_insert_idx + 1) % SPI0_TX_BUFFER_SIZE;
> >
> >   if (temp == spi0_tx_extract_idx)
> >     return -1;                          // no room
> >
> >   cpsr = disableIRQ();                  // disable global interrupts
> >   S0SPCR &= ~SPCR_SPIE;                 // disable TX interrupts
> >   restoreIRQ(cpsr);                     // restore global interrupts
> >
> >   // check if in process of sending data
> >   if (spi0_tx_running){
> >     // add to queue
> >     spi0_tx_buffer[spi0_tx_insert_idx] = (uint8_t)ch;
> >     spi0_tx_insert_idx = temp;
> >   }
> >   else{
> >     // set running flag and write to output register   
> >     spi0_tx_running = 1;
> >     S0SPDR = (uint8_t)ch;
> >   }
> >   cpsr = disableIRQ();                  // disable global interrupts
> >   S0SPCR |= SPCR_SPIE;                  // enable TX interrupts
> >   restoreIRQ(cpsr);                     // restore global interrupts
> >
> >   return (uint8_t)ch;
> > }
> >
> > and finally, the ISR that never fires...
> > void spi0ISR(void)
> > {
> >   // perform proper ISR entry so thumb-interwork works properly
> >   ISR_ENTRY();
> >
> >   // check if more data to send
> >   if (spi0_tx_insert_idx != spi0_tx_extract_idx){
> >     S0SPDR = spi0_tx_buffer[spi0_tx_extract_idx++];
> >     spi0_tx_extract_idx %= SPI0_TX_BUFFER_SIZE;
> >   }
> >   else{ // No more to transmit
> >     S0SPCR &= ~SPCR_SPIE;
> >     spi0_tx_running = 0;
> >   }
> >  
> >   S0SPINT = 1; 
> >   VICVectAddr = 0x00000000;  
> >
> >   ISR_EXIT();
> > }
> >
> > It seems like it should be something simple.  Everything looks okay,
> > but the ISR never fires.
> >
> > Thanks,
> >
> > Gary
> >
>
>
>
>
>
>
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I've been able to configure and use the uart and timer interrupts no
problem.  That's why this SPI interrupt not firing has me so stumped.

Gary

--- In lpc2000@yahoogroups.com, "drb5599" <dbutler@c...> wrote:

>
> I believe you Gary.  I had the same problem.  I have been using the 
> MCB2130 (2138) and LPC2131 (my hardware).  I finally gave up on the 
> SPI interrupt and now just use polling.  Not very efficient, but in 
> my application it is acceptable.
> Strange thing to me was the fact that it is just the SPI interrupt 
> that has caused problems.  I have been able to configure and use 
> every other interrupt available, no problem.
> 
> -Dave
> 
> 
> --- In lpc2000@yahoogroups.com, "ee_gary" <ee_gary@y...> wrote:
> >
> > --- In lpc2000@yahoogroups.com, Sten <list@n...> wrote:
> > >
> > > ee_gary wrote:
> > > > Long time lurker, first time poster...
> > > > 
> > > > I've set the SPIE bit in the Control Register.  I can see the 
> SPIF bit
> > > > get set in the Status Register.  However, I do NOT see the SPI
> > > > Interrupt bit get set in the Interrupt Register.  Shouldn't 
> this occur
> > > > as soon as the SPIF bit is set, regardless of how the VIC is 
> set up? 
> > > > I have the VIC set up "correctly", but the ISR never executes
> > > > (presumably because the SPI Interrupt never fires).  I've had
> > > > interrupts working correctly for UART0 and a timer, so I know 
> that
> > > > interrupts can work (they just aren't in this occasion).
> > > > 
> > > > I can do non-interrupt SPI transmits (i.e. the 1st byte of an
> > > > interrupt-based multibye transfer) so I know the hardware is ok 
> (SSEL
> > > > = 1).  I've duplicated this on the MCB2130 and a LPC2214 dev 
> board.
> > > > 
> > > > Any insight from those that have implemented interrupt based 
> SPI is
> > > > appreciated.
> > > > 
> > > > Stumped in Seattle...
> > > > 
> > > 
> > > Please can you send a small portion of source code? It sounds
> > unbelievable.
> > > 
> > >   Sten
> > > 
> > > -- 
> > > /************************************************
> > >  Do you need a tiny and efficient real time
> > >  operating system (RTOS) with a preemtive
> > >  multitasking for LPC2000 or AT91SAM7?
> > > 
> > >    http://nanortos.net-attack.de/
> > > 
> > >  Or some open-source tools and code for LPC2000?
> > > 
> > >    http://www.net-attack.de/
> > > 
> > > ************************************************/
> > >
> > 
> > It'd be my pleasure.  Here's the init function:
> > void spi0Init(void)
> > {
> >   // Set port pins for SPI0
> >   PINSEL0 = (PINSEL0 & ~S0_PINMASK) | S0_PINSEL;
> > 
> >   // Set SPI Registers
> >   S0SPCR = 0;           // Clear all bits
> >   S0SPCR |= SPCR_CPHA;  // Data sampled on rising edge
> >   S0SPCR |= SPCR_CPOL;	// SCK active low
> >   S0SPCR |= SPCR_MSTR;	// Master mode
> > 
> >   S0SPSR;         // Cleared by a read of this register
> >   S0SPDR;         // Cleared by a read of this register
> >   S0SPCCR = 128;  // 8 is max speed
> >   S0SPINT = 1;    // Cleared by writing a 1 to it
> > 
> >   // initialize the interrupt vector
> >   VICIntSelect = 0;  // Select IRQ
> >   VICIntEnable = 0x00000400;
> >   VICVectAddr0 = (unsigned long)spi0ISR;
> >   VICVectCntl0 = 0x0000002A;
> > 								
> 	
> >   // initialize the transmit data queue
> >   spi0_tx_extract_idx = spi0_tx_insert_idx = 0;
> >   spi0_tx_running = 0;
> > }
> > 
> > and the transmit function:
> > int spi0Putch(int ch)
> > {
> >   uint16_t temp;
> >   unsigned cpsr;
> > 
> >   temp = (spi0_tx_insert_idx + 1) % SPI0_TX_BUFFER_SIZE;
> > 
> >   if (temp == spi0_tx_extract_idx)
> >     return -1;                          // no room
> > 
> >   cpsr = disableIRQ();                  // disable global interrupts
> >   S0SPCR &= ~SPCR_SPIE;                 // disable TX interrupts
> >   restoreIRQ(cpsr);                     // restore global interrupts
> > 
> >   // check if in process of sending data
> >   if (spi0_tx_running){
> >     // add to queue
> >     spi0_tx_buffer[spi0_tx_insert_idx] = (uint8_t)ch;
> >     spi0_tx_insert_idx = temp;
> >   }
> >   else{
> >     // set running flag and write to output register    
> >     spi0_tx_running = 1;
> >     S0SPDR = (uint8_t)ch;
> >   }
> >   cpsr = disableIRQ();                  // disable global interrupts
> >   S0SPCR |= SPCR_SPIE;                  // enable TX interrupts
> >   restoreIRQ(cpsr);                     // restore global interrupts
> > 
> >   return (uint8_t)ch;
> > }
> > 
> > and finally, the ISR that never fires...
> > void spi0ISR(void)
> > {
> >   // perform proper ISR entry so thumb-interwork works properly
> >   ISR_ENTRY();
> > 
> >   // check if more data to send
> >   if (spi0_tx_insert_idx != spi0_tx_extract_idx){
> >     S0SPDR = spi0_tx_buffer[spi0_tx_extract_idx++];
> >     spi0_tx_extract_idx %= SPI0_TX_BUFFER_SIZE;
> >   }
> >   else{ // No more to transmit
> >     S0SPCR &= ~SPCR_SPIE;
> >     spi0_tx_running = 0;
> >   }
> >   
> >   S0SPINT = 1;  
> >   VICVectAddr = 0x00000000;   
> > 
> >   ISR_EXIT();
> > }
> > 
> > It seems like it should be something simple.  Everything looks okay,
> > but the ISR never fires.
> > 
> > Thanks,
> > 
> > Gary
> >
>

> Same experience here. Tried to do the interrupt thing, now I 
> just start the SPI transfer, do some other stuff and then 
> poll until the transfer is ready. Is there anybody that has 
> used the SPI interrupt successfully???

I use SPI interrupts for SPI transactions and haven't run into any
issues as yet.
Mind you it's on a lpc2124, not an lpc2138. My SPI module is part of the
lpc newlib extensions.

> Richard Duits.
> 
> 
> drb5599 wrote:
> 
> > I believe you Gary.  I had the same problem.  I have been using the 
> > MCB2130 (2138) and LPC2131 (my hardware).  I finally gave up on the 
> > SPI interrupt and now just use polling.  Not very 
> efficient, but in my 
> > application it is acceptable.
> > Strange thing to me was the fact that it is just the SPI interrupt 
> > that has caused problems.  I have been able to configure 
> and use every 
> > other interrupt available, no problem.
> >
> > -Dave
> >
> >
> > --- In lpc2000@yahoogroups.com, "ee_gary" <ee_gary@y...> wrote:
> > >
> > > --- In lpc2000@yahoogroups.com, Sten <list@n...> wrote:
> > > >
> > > > ee_gary wrote:
> > > > > Long time lurker, first time poster...
> > > > >
> > > > > I've set the SPIE bit in the Control Register.  I can see the
> > SPIF bit
> > > > > get set in the Status Register.  However, I do NOT 
> see the SPI 
> > > > > Interrupt bit get set in the Interrupt Register.  Shouldn't
> > this occur
> > > > > as soon as the SPIF bit is set, regardless of how the VIC is
> > set up?
> > > > > I have the VIC set up "correctly", but the ISR never executes 
> > > > > (presumably because the SPI Interrupt never fires).  I've had 
> > > > > interrupts working correctly for UART0 and a timer, so I know
> > that
> > > > > interrupts can work (they just aren't in this occasion).
> > > > >
> > > > > I can do non-interrupt SPI transmits (i.e. the 1st byte of an 
> > > > > interrupt-based multibye transfer) so I know the 
> hardware is ok
> > (SSEL
> > > > > = 1).  I've duplicated this on the MCB2130 and a LPC2214 dev
> > board.
> > > > >
> > > > > Any insight from those that have implemented interrupt based
> > SPI is
> > > > > appreciated.
> > > > >
> > > > > Stumped in Seattle...
> > > > >
> > > >
> > > > Please can you send a small portion of source code? It sounds
> > > unbelievable.
> > > >
> > > >   Sten
> > > >
> > > > --
> > > > /************************************************
> > > >  Do you need a tiny and efficient real time  operating system 
> > > > (RTOS) with a preemtive  multitasking for LPC2000 or AT91SAM7?
> > > >
> > > >    http://nanortos.net-attack.de/
> > > >
> > > >  Or some open-source tools and code for LPC2000?
> > > >
> > > >    http://www.net-attack.de/
> > > >
> > > > ************************************************/
> > > >
> > >
> > > It'd be my pleasure.  Here's the init function:
> > > void spi0Init(void)
> > > {
> > >   // Set port pins for SPI0
> > >   PINSEL0 = (PINSEL0 & ~S0_PINMASK) | S0_PINSEL;
> > >
> > >   // Set SPI Registers
> > >   S0SPCR = 0;           // Clear all bits
> > >   S0SPCR |= SPCR_CPHA;  // Data sampled on rising edge
> > >   S0SPCR |= SPCR_CPOL;      // SCK active low
> > >   S0SPCR |= SPCR_MSTR;      // Master mode
> > >
> > >   S0SPSR;         // Cleared by a read of this register
> > >   S0SPDR;         // Cleared by a read of this register
> > >   S0SPCCR = 128;  // 8 is max speed
> > >   S0SPINT = 1;    // Cleared by writing a 1 to it
> > >
> > >   // initialize the interrupt vector
> > >   VICIntSelect = 0;  // Select IRQ
> > >   VICIntEnable = 0x00000400;
> > >   VICVectAddr0 = (unsigned long)spi0ISR;
> > >   VICVectCntl0 = 0x0000002A;
> > >                                                
> >      
> > >   // initialize the transmit data queue
> > >   spi0_tx_extract_idx = spi0_tx_insert_idx = 0;
> > >   spi0_tx_running = 0;
> > > }
> > >
> > > and the transmit function:
> > > int spi0Putch(int ch)
> > > {
> > >   uint16_t temp;
> > >   unsigned cpsr;
> > >
> > >   temp = (spi0_tx_insert_idx + 1) % SPI0_TX_BUFFER_SIZE;
> > >
> > >   if (temp == spi0_tx_extract_idx)
> > >     return -1;                          // no room
> > >
> > >   cpsr = disableIRQ();                  // disable global 
> interrupts
> > >   S0SPCR &= ~SPCR_SPIE;                 // disable TX interrupts
> > >   restoreIRQ(cpsr);                     // restore global 
> interrupts
> > >
> > >   // check if in process of sending data
> > >   if (spi0_tx_running){
> > >     // add to queue
> > >     spi0_tx_buffer[spi0_tx_insert_idx] = (uint8_t)ch;
> > >     spi0_tx_insert_idx = temp;
> > >   }
> > >   else{
> > >     // set running flag and write to output register   
> > >     spi0_tx_running = 1;
> > >     S0SPDR = (uint8_t)ch;
> > >   }
> > >   cpsr = disableIRQ();                  // disable global 
> interrupts
> > >   S0SPCR |= SPCR_SPIE;                  // enable TX interrupts
> > >   restoreIRQ(cpsr);                     // restore global 
> interrupts
> > >
> > >   return (uint8_t)ch;
> > > }
> > >
> > > and finally, the ISR that never fires...
> > > void spi0ISR(void)
> > > {
> > >   // perform proper ISR entry so thumb-interwork works properly
> > >   ISR_ENTRY();
> > >
> > >   // check if more data to send
> > >   if (spi0_tx_insert_idx != spi0_tx_extract_idx){
> > >     S0SPDR = spi0_tx_buffer[spi0_tx_extract_idx++];
> > >     spi0_tx_extract_idx %= SPI0_TX_BUFFER_SIZE;
> > >   }
> > >   else{ // No more to transmit
> > >     S0SPCR &= ~SPCR_SPIE;
> > >     spi0_tx_running = 0;
> > >   }
> > >  
> > >   S0SPINT = 1; 
> > >   VICVectAddr = 0x00000000;
> > >
> > >   ISR_EXIT();
> > > }
> > >
> > > It seems like it should be something simple.  Everything 
> looks okay, 
> > > but the ISR never fires.
> > >
> > > Thanks,
> > >
> > > Gary
> > >
> >
> >
> >
> >
> >
> >
> > SPONSORED LINKS
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> > Same experience here. Tried to do the interrupt thing, now I 
> > just start the SPI transfer, do some other stuff and then 
> > poll until the transfer is ready. Is there anybody that has 
> > used the SPI interrupt successfully???
> 
> I use SPI interrupts for SPI transactions and haven't run into any
> issues as yet. Mind you it's on a lpc2124, not an lpc2138. My SPI
> module is part of the lpc newlib extensions.

Hey Bruce,

Care to enlighten me about that last comment.

> lpc newlib extensions

I've been meaning to go through the newlib re-entrancy configuration
etc to see what needs to be turned on for uCOS-II thread-safe usage,
and to create some sort of device operations table interface
(as per Bill Gatliff's docs from Embedded Systems Programming).
I saw a post the other day from someone at Aeolus regarding their
newlib port layer (perhaps that was you)

http://www.aeolusdevelopment.com/Articles/download.html

anyways, if you have a nice clean way of implementing a device
layer, let us know and people can contribute with a common
interface.

Cheers
Dave

> > > Same experience here. Tried to do the interrupt thing, now I just 
> > > start the SPI transfer, do some other stuff and then poll 
> until the 
> > > transfer is ready. Is there anybody that has used the SPI 
> interrupt 
> > > successfully???
> > 
> > I use SPI interrupts for SPI transactions and haven't run into any 
> > issues as yet. Mind you it's on a lpc2124, not an lpc2138. My SPI 
> > module is part of the lpc newlib extensions.
> 
> Hey Bruce,
> 
> Care to enlighten me about that last comment.
> 
> > lpc newlib extensions
> 
> I've been meaning to go through the newlib re-entrancy 
> configuration etc to see what needs to be turned on for 
> uCOS-II thread-safe usage, and to create some sort of device 
> operations table interface (as per Bill Gatliff's docs from 
> Embedded Systems Programming).
> I saw a post the other day from someone at Aeolus regarding 
> their newlib port layer (perhaps that was you)
> 
> http://www.aeolusdevelopment.com/Articles/download.html
> 
> anyways, if you have a nice clean way of implementing a 
> device layer, let us know and people can contribute with a 
> common interface.

No it wasn't me. It was the Robert Ansett, the compiler of newlib_lpc.
I'm not sure if he has rolled my SPI module into his latest newlib_lpc
release as yet, but if necessary I can email it to you.
Yes, it is good to conform to a common interface, and due to other
newlib_lpc modules being available it significantly cut down my overall
effort, even though I coded the SPI, and added some zero-copy options to
the the uart modules.
The easiest way to code a new module is to copy an existing one and
modify the bottom end. In this way I have also created an IIC module,
but haven't had a chance to test as yet. Robert also has a copy of that,
but beware it is probably buggy.

Cheers,
Bruce

> > Care to enlighten me about that last comment....
> >  <snip>

> 
> No it wasn't me. It was the Robert Ansett, the compiler of newlib_lpc.
> I'm not sure if he has rolled my SPI module into his latest newlib_lpc
> release as yet, but if necessary I can email it to you.
> Yes, it is good to conform to a common interface, and due to other
> newlib_lpc modules being available it significantly cut down my overall
> effort, even though I coded the SPI, and added some zero-copy options to
> the the uart modules.
> The easiest way to code a new module is to copy an existing one and
> modify the bottom end. In this way I have also created an IIC module,
> but haven't had a chance to test as yet. Robert also has a copy of that,
> but beware it is probably buggy.
> 
> Cheers,
> Bruce

Great, thanks for the feedback. Perhaps I'll get to play with this
stuff over the weekend and get to look at Robert's stuff.

Cheers
Dave

At 12:52 PM 10/13/05 +1000, Bruce Paterson wrote:
> > Hey Bruce,
> >
> > Care to enlighten me about that last comment.
> >
> > > lpc newlib extensions
> >
> > I've been meaning to go through the newlib re-entrancy
> > configuration etc to see what needs to be turned on for
> > uCOS-II thread-safe usage, and to create some sort of device
> > operations table interface (as per Bill Gatliff's docs from
> > Embedded Systems Programming).
> > I saw a post the other day from someone at Aeolus regarding
> > their newlib port layer (perhaps that was you)
> >
> > http://www.aeolusdevelopment.com/Articles/download.html
> >
> > anyways, if you have a nice clean way of implementing a
> > device layer, let us know and people can contribute with a
> > common interface.
>
>No it wasn't me. It was the Robert Ansett, the compiler of newlib_lpc.
>I'm not sure if he has rolled my SPI module into his latest newlib_lpc
>release as yet, but if necessary I can email it to you.
>Yes, it is good to conform to a common interface, and due to other
>newlib_lpc modules being available it significantly cut down my overall
>effort, even though I coded the SPI, and added some zero-copy options to
>the the uart modules.


It was probably my post you saw David.  And I haven't rolled Bruce's stuff 
in yet.  I've been distracted with clients work.  It is high on my todo 
list as well as a way to allow contributed code out in the wild more 
quickly especially drivers so they don't get stalled like this.  It'll 
probably be simple but I have to actually get it done.

I haven't explicitly addressed re-entrancy but I did try to structure 
things so it could be taken care of in the future.  As far as how 
successful that's been well the proof of the pudding will be in the eating.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/

Hey Robert,
> 
> It was probably my post you saw David.  And I haven't rolled 
> Bruce's stuff 
> in yet.  I've been distracted with clients work.  It is high on my todo 
> list as well as a way to allow contributed code out in the wild more 
> quickly especially drivers so they don't get stalled like this.  It'll 
> probably be simple but I have to actually get it done.
> 
> I haven't explicitly addressed re-entrancy but I did try to structure 
> things so it could be taken care of in the future.  As far as how 
> successful that's been well the proof of the pudding will be in 
> the eating.

If I get a chance to look at it, and can either contribute bug
fixes, or new drivers, I will.

I haven't looked at your driver layer, but out of interest, what
did you base it on? I've got an Altera Stratix II DSP kit, and
the Altera NIOS II development software comes with a nice driver 
layer for newlib and their HAL, which is then interfaced to uCOS-II.
There is also an eCOS port for the NIOS II processor, but I'm not 
sure if the HAL used there is identical. I've only just started
tinkering with that kit - problem was you need an FPGA implementation
of the processor before you can even start, and it was
missing from their 1.0.0 CD! I've just received the 1.1.0 CD and
the 'standard' processor reference design is there.

Seems like newlib has a new driver layer ported to every
time someone decides it needs one. I just want one layer
thats fairly processor agnositic (ie a HAL) so that I can run
similar application tests on the various processor to
see what meets my needs.

Thanks!
Dave

Hey Robert,
>
> " 'Freedom' has no meaning of itself.  There are always
> restrictions,   be
> they legal, genetic, or physical.  If you don't believe me, try to chew a
> radio signal. "  -- Kelvin Throop, III

or 'look through a radio telescope'

people are always disappointed when they find out that they can't.

www.mmarray.org
www.ovro.caltech.edu


Cheers
Dave

Senior Scientist
Caltech's Owens Valley Radio Observatory.

--- In lpc2000@yahoogroups.com, "Bruce Paterson" <bruce.paterson@b...>
wrote:
>
> > > > Same experience here. Tried to do the interrupt thing, now I just 
> > > > start the SPI transfer, do some other stuff and then poll 
> > until the 
> > > > transfer is ready. Is there anybody that has used the SPI 
> > interrupt 
> > > > successfully???
> > > 
> > > I use SPI interrupts for SPI transactions and haven't run into any 
> > > issues as yet. Mind you it's on a lpc2124, not an lpc2138. My SPI 
> > > module is part of the lpc newlib extensions.
> > 
> > Hey Bruce,
> > 
> > Care to enlighten me about that last comment.
> > 
> > > lpc newlib extensions
> > 
> > I've been meaning to go through the newlib re-entrancy 
> > configuration etc to see what needs to be turned on for 
> > uCOS-II thread-safe usage, and to create some sort of device 
> > operations table interface (as per Bill Gatliff's docs from 
> > Embedded Systems Programming).
> > I saw a post the other day from someone at Aeolus regarding 
> > their newlib port layer (perhaps that was you)
> > 
> > http://www.aeolusdevelopment.com/Articles/download.html
> > 
> > anyways, if you have a nice clean way of implementing a 
> > device layer, let us know and people can contribute with a 
> > common interface.
> 
> No it wasn't me. It was the Robert Ansett, the compiler of newlib_lpc.
> I'm not sure if he has rolled my SPI module into his latest newlib_lpc
> release as yet, but if necessary I can email it to you.
> Yes, it is good to conform to a common interface, and due to other
> newlib_lpc modules being available it significantly cut down my overall
> effort, even though I coded the SPI, and added some zero-copy options to
> the the uart modules.
> The easiest way to code a new module is to copy an existing one and
> modify the bottom end. In this way I have also created an IIC module,
> but haven't had a chance to test as yet. Robert also has a copy of that,
> but beware it is probably buggy.
> 
> Cheers,
> Bruce
>

I'd be interested in the newlib_lpc SPI module as well (interrupt
driven, of couse).

Thanks,

Gary

I'm a newbie, so don't take my comment too seriously, but... why are 
you disabling SPIE interrupts in your enqueue function? Couldn't this 
adversedly affect the expected behavior? If your intention is to 
protect the buffer pointers while these are being updated, I'd go for 
a full IRQ disable rather than a targeted masking; of course this is 
acceptable only if you can afford a small lag between interrupts. 
Also, as I read the pseudo-code example in the LPC2138 user's manual, 
the SPI control register should be written to before writing onto the 
data register (which in some way may suggest that it should not be 
written to after the data is set in the shift register). Yhis is what 
I'd do:

int spi0Putch(int ch)
{
uint16_t temp;
unsigned cpsr;

cpsr = disableIRQ(); // disable global interrupts before atempting to 
read spi0_tx_insert_idx (in case of multitasking being used)
// Avoid using modulo operator in ARM7 for performance reasons
//temp = (spi0_tx_insert_idx + 1) % SPI0_TX_BUFFER_SIZE;
temp = spi0_tx_insert_idx + 1;
if( temp == SPI0_TX_BUFFER_SIZE ) temp = 0;
if (temp == spi0_tx_extract_idx)
{
  restoreIRQ(cpsr); // restore global interrupts
  return -1; // no room
}

// check if in process of sending data
if (spi0_tx_running){
  // add to queue
  spi0_tx_buffer[spi0_tx_insert_idx] = (uint8_t)ch;
  spi0_tx_insert_idx = temp;
}
else{
  // set running flag and write to output register
  S0SPCR |= SPCR_SPIE; // enable TX interrupts before writing to 
SOSPDR
  spi0_tx_running = 1;
  S0SPDR = (uint8_t)ch;
}
restoreIRQ(cpsr); // restore global interrupts

return (uint8_t)ch;
}


Hope this helps.

Guille

--- In lpc2000@yahoogroups.com, "ee_gary" <ee_gary@y...> wrote:
>
> --- In lpc2000@yahoogroups.com, Sten <list@n...> wrote:
> >
> > ee_gary wrote:
> > > Long time lurker, first time poster...
> > > 
> > > I've set the SPIE bit in the Control Register.  I can see the 
SPIF bit
> > > get set in the Status Register.  However, I do NOT see the SPI
> > > Interrupt bit get set in the Interrupt Register.  Shouldn't 
this occur
> > > as soon as the SPIF bit is set, regardless of how the VIC is 
set up? 
> > > I have the VIC set up "correctly", but the ISR never executes
> > > (presumably because the SPI Interrupt never fires).  I've had
> > > interrupts working correctly for UART0 and a timer, so I know 
that
> > > interrupts can work (they just aren't in this occasion).
> > > 
> > > I can do non-interrupt SPI transmits (i.e. the 1st byte of an
> > > interrupt-based multibye transfer) so I know the hardware is ok 
(SSEL
> > > = 1).  I've duplicated this on the MCB2130 and a LPC2214 dev 
board.
> > > 
> > > Any insight from those that have implemented interrupt based 
SPI is

> > > appreciated.
> > > 
> > > Stumped in Seattle...
> > > 
> > 
> > Please can you send a small portion of source code? It sounds
> unbelievable.
> > 
> >   Sten
> > 
> > -- 
> > /************************************************
> >  Do you need a tiny and efficient real time
> >  operating system (RTOS) with a preemtive
> >  multitasking for LPC2000 or AT91SAM7?
> > 
> >    http://nanortos.net-attack.de/
> > 
> >  Or some open-source tools and code for LPC2000?
> > 
> >    http://www.net-attack.de/
> > 
> > ************************************************/
> >
> 
> It'd be my pleasure.  Here's the init function:
> void spi0Init(void)
> {
>   // Set port pins for SPI0
>   PINSEL0 = (PINSEL0 & ~S0_PINMASK) | S0_PINSEL;
> 
>   // Set SPI Registers
>   S0SPCR = 0;           // Clear all bits
>   S0SPCR |= SPCR_CPHA;  // Data sampled on rising edge
>   S0SPCR |= SPCR_CPOL;	// SCK active low
>   S0SPCR |= SPCR_MSTR;	// Master mode
> 
>   S0SPSR;         // Cleared by a read of this register
>   S0SPDR;         // Cleared by a read of this register
>   S0SPCCR = 128;  // 8 is max speed
>   S0SPINT = 1;    // Cleared by writing a 1 to it
> 
>   // initialize the interrupt vector
>   VICIntSelect = 0;  // Select IRQ
>   VICIntEnable = 0x00000400;
>   VICVectAddr0 = (unsigned long)spi0ISR;
>   VICVectCntl0 = 0x0000002A;
> 								
	
>   // initialize the transmit data queue
>   spi0_tx_extract_idx = spi0_tx_insert_idx = 0;
>   spi0_tx_running = 0;
> }
> 
> and the transmit function:
> int spi0Putch(int ch)
> {
>   uint16_t temp;
>   unsigned cpsr;
> 
>   temp = (spi0_tx_insert_idx + 1) % SPI0_TX_BUFFER_SIZE;
> 
>   if (temp == spi0_tx_extract_idx)
>     return -1;                          // no room
> 
>   cpsr = disableIRQ();                  // disable global interrupts
>   S0SPCR &= ~SPCR_SPIE;                 // disable TX interrupts
>   restoreIRQ(cpsr);                     // restore global interrupts
> 
>   // check if in process of sending data
>   if (spi0_tx_running){
>     // add to queue
>     spi0_tx_buffer[spi0_tx_insert_idx] = (uint8_t)ch;
>     spi0_tx_insert_idx = temp;
>   }
>   else{
>     // set running flag and write to output register    
>     spi0_tx_running = 1;
>     S0SPDR = (uint8_t)ch;
>   }
>   cpsr = disableIRQ();                  // disable global interrupts
>   S0SPCR |= SPCR_SPIE;                  // enable TX interrupts
>   restoreIRQ(cpsr);                     // restore global interrupts
> 
>   return (uint8_t)ch;
> }
> 
> and finally, the ISR that never fires...
> void spi0ISR(void)
> {
>   // perform proper ISR entry so thumb-interwork works properly
>   ISR_ENTRY();
> 
>   // check if more data to send
>   if (spi0_tx_insert_idx != spi0_tx_extract_idx){
>     S0SPDR = spi0_tx_buffer[spi0_tx_extract_idx++];
>     spi0_tx_extract_idx %= SPI0_TX_BUFFER_SIZE;
>   }
>   else{ // No more to transmit
>     S0SPCR &= ~SPCR_SPIE;
>     spi0_tx_running = 0;
>   }
>   
>   S0SPINT = 1;  
>   VICVectAddr = 0x00000000;   
> 
>   ISR_EXIT();
> }
> 
> It seems like it should be something simple.  Everything looks okay,
> but the ISR never fires.
> 
> Thanks,
> 
> Gary
>