Lpc2000

Good advice, Richard. I'll take it. Thanks.

--- In lpc2000@yahoogroups.com, Richard Duits <yahoo@r...> wrote:
>
> It's almost impossible to miss an interrupt. Your only worry is 
that you 
> respond to the interrupt in time. For example the UART can only 
buffer a 
> number of bytes (16 if you use the fifo). If you respond to the 
UART 
> receive interrupt to late, you get an overrun and data is lost. So 
you 
> cannot miss an interrupt, but be carefull that you do not write to 
much 
> code in the interupt handlers. Very long interrupt handlers can 
delay 
> another interrupt so long that something may go wrong. This is 
called a 
> deadline.
> 
> Richard Duits
> 
> 
> 
> Guillermo Prandi wrote:
> 
> > Thanks, Richard.
> >
> > So, if I understand correctly, if I don't clear the interrupts in 
my
> > interrupt handler (or a new interrupt happens while at the 
handler)
> > the handler will be called again as soon as I restore the CSPR
> > register, which should happen at my final MOVS PC,LR?
> >
> > I'm worried about inadvertently writing code that would miss
> > interrupts. As I get from your explanation, that's easy to avoid.
> >
> > Guille
> >
> > --- In lpc2000@yahoogroups.com, Richard Duits <yahoo@r...> wrote:
> > >
> > > With everything that generates an interrupt, you have to clear 
the
> > > interrupt by reading or writing to a register. For example with 
the
> > UART
> > > you clear a data ready interrupt by reading the data. If you 
cannot
> > > clear the interrupt (for example a UART transmit holding 
register
> > emty
> > > while you have nothing to send), you disable it. If you do not
> > clear or
> > > disable the interrupt, the interrupt will be called again
> > immidiately
> > > after you return from it.
> > >
> > > Level sensitive interrupts are active if the input pin is low 
(high
> > if
> > > INTPOLAR bit is set), edge sensitive interrupts become active on
> > the
> > > high to low transition (if INTPOLAR bit is clear) of the input 
pin.
> > All
> > > internal interrupts are level sensitive. External interrupts are
> > cached
> > > and converted to level senstive interrupt by the external 
interrupt
> > > controller.
> > >
> > >
> > >
> > > Guillermo Prandi wrote:
> > >
> > > > Hi! I read every doc I've found and I couldn't get a detailed
> > > > description of the interrupt mechanism in the LPC2XXX. In
> > particular,
> > > > I'm looking for the following:
> > > >
> > > > - What happens to interrupts while they're disabled? Do they
> > > > get "cached"? I mean, if I'm in the middle of processing a 
UART0
> > > > interrupt and UART1 receives a new character, I'd probably 
have
> > the
> > > > interrupts disabled. Will I miss the interrupt?
> > > >
> > > > - Provided the interrupts get chached while disabled 
somehow...
> > That
> > > > would mean that they will trigger as soon as they're enabled,
> > isn't it?
> > > > I plan to keep interrupts disabled while processing other
> > interrupts;
> > > > could that work?
> > > >
> > > > - What's the exact difference between edge and level triggered
> > > > interrupts?
> > > >
> > > > Thanks in advance
> > > >
> > > >
> > > >
> > > >
> > > >
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t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
> > rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
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t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
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icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
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ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
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