Lpc2000

>We had pulled P0.31 down because it was the enable for a 485
>transciever and needed to be low during reset.
>
>Turns out there is an 'undocumented feature' on some of the LPC
>parts including the 2138 that will disable JTAG if P0.31 is low during
>reset. We all know about RTCLK needing to be high during reset
>for JTAG because it's documented, but P0.31 functions exactly the
>same way.

I am not sure as to how one can guarantee that P0.31 is indeed pulled high
during reset to enable JTAG debugging. I assume this would have to be done
in software running on the device, but then to get that software into
memory requires use of the JTAG port. Seems like a chicken and egg
problem. Am I missing something?
Thanks,
-BNP

On Mon, 7 Nov 2005 12:43:22 -0500 (EST), Bhanu Nagendra Pisupati wrote:

>>We had pulled P0.31 down because it was the enable for a 485
>>transciever and needed to be low during reset.
>>
>>Turns out there is an 'undocumented feature' on some of the LPC
>>parts including the 2138 that will disable JTAG if P0.31 is low during
>>reset. We all know about RTCLK needing to be high during reset
>>for JTAG because it's documented, but P0.31 functions exactly the
>>same way.

>I am not sure as to how one can guarantee that P0.31 is indeed pulled high
>during reset to enable JTAG debugging. I assume this would have to be done
>in software running on the device, but then to get that software into
>memory requires use of the JTAG port. Seems like a chicken and egg
>problem. Am I missing something?
>Thanks,
>-BNP


Put a pull-up resistor on the pin.  It's configured as an input as the
processor comes out of reset.  You can set it to being an output pulled
low in your startup code.  A better solution would be to move the functionality
to a different pin then it wouldn't hog the 485 bus every time the system was
reset.

Regards
-Bill Knight
R O SoftWare &
http://www.theARMPatch.com

What chips does this apply to?

Gus
--- In lpc2000@yahoogroups.com, "Bill Knight" <BillK@t...> wrote:
>
> On Mon, 7 Nov 2005 12:43:22 -0500 (EST), Bhanu Nagendra Pisupati 
wrote:
> 
> >>We had pulled P0.31 down because it was the enable for a 485
> >>transciever and needed to be low during reset.
> >>
> >>Turns out there is an 'undocumented feature' on some of the LPC
> >>parts including the 2138 that will disable JTAG if P0.31 is low 
during
> >>reset. We all know about RTCLK needing to be high during reset
> >>for JTAG because it's documented, but P0.31 functions exactly the
> >>same way.
> 
> >I am not sure as to how one can guarantee that P0.31 is indeed 
pulled high
> >during reset to enable JTAG debugging. I assume this would have 
to be done
> >in software running on the device, but then to get that software 
into
> >memory requires use of the JTAG port. Seems like a chicken and egg
> >problem. Am I missing something?
> >Thanks,
> >-BNP
> 
> 
> Put a pull-up resistor on the pin.  It's configured as an input as 
the
> processor comes out of reset.  You can set it to being an output 
pulled
> low in your startup code.  A better solution would be to move the 
functionality
> to a different pin then it wouldn't hog the 485 bus every time the 
system was

> reset.
> 
> Regards
> -Bill Knight
> R O SoftWare &
> http://www.theARMPatch.com
>