bit order issues in EmbeddedICE
2005-11-10 by Bhanu Nagendra Pisupati
Hello, I would like to clarify the byte order semantics in using the EmbeddedICE block in lpc parts. Specifically, my question relates to writing to the debug control register using the scan chain #2 register of JTAG. The documentation states that data to the scan chain needs to be written as shown below: TDI -> R/Wbit RegAddress[4..0] Data[0] ...... Data[31] -> TDO The debug control register however is only 5 bits long. So would these 5 bits have to be included within < Data[0] ... Data[4] > or within < Data[28] ... Data[31] > ? Also, would the data be written as MSB of data first (closest to TDO) or the other way around? These seem like issues that the documentation would address, but even after a thorough reading the questions seemed unanswered. Thanks, -BNP