Lpc2000

Hello,

Can sombody explain to me, how it possible that the LPC21xx with MAM
hardware only delivers approx 20 MIPS with a 60 MHz clock, and an
ANALOG DEVICES ADuC7xxx (with the same core?) is quoted to deliver 40
MIPS with a 40 MHz clock?

If the core needs several clock pulses to execute an instruction, why
bother using the MAM hardware. The flash delivers 128 bits (4
instructio ns) at 20 MHz (Did I misread the manual?)

Please explain.

Thanks

Hi,

by definition of ARM themselves, the ARM7 can deliver 0.9 MIPS / MHz
so, the 40 MIPS @ 40 MHz is not what Analog claims because it is
running at 44 MHz (page 83 od ADuC rev 0 document), nevertheless the
maximum speed for the Flash is specified for . Secondly, I do not know
where you read anything about 20 MIPS in any of the LPC2000 documents.
It delivers (from Flash) definitely more than 50 ARM-MIPS not just
THUMB-MIPS. Others quote MIPS in THUMB mode, this is about 30-40% less
performance per instruction. 

The MAM has to be programmed based on the operating speed. If MAMTIM
is greater one, there will be a delay for the first fetch after a
branch. The MAM fetches 128 bit = 4 ARM instructions = 8 THUMB
instructions every time it does a fetch. I saw a presentation recently
talking about the bandwidth of Flash, the LPC2000 can fetch 128-bit
every 50 ns, so there is enough bandwidth to execute full speed after
the first fetch until the next branch. 

Of the datasheet:
Sixty-two kilobytes of Flash/EE memory are available to the
user as code and nonvolatile data memory. There is no
distinction between data and program as ARM code shares the
same space. The real width of the Flash/EE memory is 16 bits,
which means that in ARM mode (32-bit instruction), two
accesses to the Flash/EE are necessary for each instruction
fetch. It is therefore recommended to use thumb mode when
executing from Flash/EE memory for optimum access speed.
The maximum access speed for the Flash/EE memory is 41.78
MHz in thumb mode and 20.89 MHz in full ARM mode.
-----------------------------------------------------
at another location in the DS this statement can be found
----------
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 22 ns, execution from Flash/EE cannot be done in
one cycle (as can be done from SRAM when CD Bit = 0).
-----------
This would indicate 45.45 MHz

So the so called 40 MIPS are THUMB MIPS versus more than 50 ARM-MIPS
on the LPC2000. This is more than 50% additional performance for the
LPC2000 is both are executing in the fastest mode. 

hth, Bob


--- In lpc2000@yahoogroups.com, "rggmns" <rggmns@y...> wrote:

>
> Hello,
> 
> Can sombody explain to me, how it possible that the LPC21xx with MAM
> hardware only delivers approx 20 MIPS with a 60 MHz clock, and an
> ANALOG DEVICES ADuC7xxx (with the same core?) is quoted to deliver 40
> MIPS with a 40 MHz clock?
> 
> If the core needs several clock pulses to execute an instruction, why
> bother using the MAM hardware. The flash delivers 128 bits (4
> instructio ns) at 20 MHz (Did I misread the manual?)
> 
> Please explain.
> 
> Thanks
>