Lpc2000

Robert

The LPC2000 external interrupts are not good for many typical single 
chip apps. Level triggered interrupts are not useful. Typically one 
would want to monitor changes on a signal from some external device 
clocking at it own rate.  Conversion to edge triggered is messy and 
involves another port line (to reset the D flip-flops).

I would like to suggest:
    All GPIO lines can have edge triggered interrupts (or at least 8 of 
them)
    2 (or 1) registers be set aside for interrupt control on GPIO pins. 
This gives 4 interrupt options per pin:

    00 No Interrupt from this pin
    01 Interupt on rising edge
    10 Interupt of falling edge
    11 Interupt on either edge.

    Another 2 (or 1) registers are setaside for GPIO interrupt status

    00 No interupt has occured in this pin
    01 a rising edge has been detected since this register was last read
    10 a falling edge has been detected since this register was last read
    11 both rising and falling edges (glitch) have been detected since 
this register was last read

Reading the GPIO interupt status register clears it to zero (completeing 
the interrupt servicing)

I don't know if there are any instances where level triggered external 
interrupts are preferrable to edge triggered.

Owen Mooney

Robert

The LPC2000 external interrupts are not good for many typical single 
chip apps. Level triggered interrupts are not useful. Typically one 
would want to monitor changes on a signal from some external device 
clocking at it own rate.  Conversion to edge triggered is messy and 
involves another port line (to reset the D flip-flops).

I would like to suggest:
   All GPIO lines can have edge triggered interrupts (or at least 8 of 
them)
   2 (or 1) registers be set aside for interrupt control on GPIO pins. 
This gives 4 interrupt options per pin:

   00 No Interrupt from this pin
   01 Interupt on rising edge
   10 Interupt of falling edge
   11 Interupt on either edge.

   Another 2 (or 1) registers are setaside for GPIO interrupt status

   00 No interupt has occured in this pin
   01 a rising edge has been detected since this register was last read
   10 a falling edge has been detected since this register was last read
   11 both rising and falling edges (glitch) have been detected since 
this register was last read

Reading the GPIO interupt status register clears it to zero (completeing 
the interrupt servicing)

I don't know if there are any instances where level triggered external 
interrupts are preferrable to edge triggered.

Owen Mooney