Lpc2000

The latest LPC2114 Data Sheet shows a Typical 1.8V current of 60 mA 
(at 25 degrees, with no active peripherals).  This is double the 
value published in the previous "prleiminary" revision.

Philips Apss:
What is the Maximum current draw (including chip-to-chip variations, 
and temperature efffects?)
What is current draw with all peripherals active?

Hello, 

You are right that the value for typical changed and unfortunately
both values did not hit the mark that we saw on the bench. While 30 mA
was too low, 60 is too high. 

Acceptance criteria for test is 70 mAs max, this includes temp
variation and chip-to-chip variations. So consider 70 mAs the max
value. Test is done with peripherals enabled, that means, the clock is
provided to most of the flipflops, which causes the current
consumption. Running the peripherals or just having them enabled does
not show a difference in power consumption of more than 5 mAs. In
fact, running them caused the current to drop a couple mAs. The
highest current we measured in characterization based on a core
voltage of 1.8V was less than 60 mAs, only if the core voltage
increases to the max. of 1.95V we saw single devices exceeding 60 mAs. 

When we really disabled the peripherals using the PCONP register and
leaving the VPB-divider at the initial divide by 4, we saw current
consumption around 35 mAs running at 60 MHz without peripherals. 

The major difference is disabling the peripherals and / or the VPD
divider for the peripheral bus. With the divider you can save approx.
10 mAs and with disabling them all approx. 15 mAs based on 60 MHz
operation.

There are so many conditions but in general, the active power is
highly dependend on your core voltage, highly dependend on your
VPD-DIV, highly dependend on the settings in PCONP, MAM-enabled, PLL
enabled.
Less dependency but still some differences for single peripherals
running or not, operating temperature.

Idle power depends mostly on the frequency provided to the
peripherals, so VPBDIV and PCONP. Disabling the PLL also makes a
significant difference. Recommendation disable PLL and set VPBDIV to 4
while disableing unused peripherals in PCONP. Measured value used
above recommendations at 10 MHz and all peripherals disabled was 2.3
mAs, same conditions 20 MHz was 4.5 mAs. With PLL enabled and running
the peripherals at max speed idel power can be around 20 mAs.

For power down current the most important factor is temperature! While
most of our devices are around 10 uAs at room temp, they are >100 uAs
at 85C.

Let me apologize for the confusion. Will work hard to do better in the
future!

btw. as a courtesy it would be nice to identify yourself by name. 

Robert


--- In lpc2000@yahoogroups.com, "lp2000c" <lp2000c@e...> wrote:

> 
> The latest LPC2114 Data Sheet shows a Typical 1.8V current of 60 mA 
> (at 25 degrees, with no active peripherals).  This is double the 
> value published in the previous "prleiminary" revision.
> 
> Philips Apss:
> What is the Maximum current draw (including chip-to-chip variations, 
> and temperature efffects?)
> What is current draw with all peripherals active?

Thanks for the excellent summary.

I realize that it is hard to specify the power consumption, because 
there are so many variables.  The "acceptance criteria," for all 
items at worst case condition is certainly valuable, and I believe 
should be added to the data sheet.  It might be helpful to include a 
couple of other "typical" values in the data sheet, and perhaps some 
graphs showing how it varies with voltage, temperature, etc.

In the meantime, I think the information in this posting should 
suffice for most people.

Do you have any Active Mode suppy current numbers for LPC2138?

As far as identifying myself, my company has a policy of engineers 
not including any identifiable information in public forums, so as 
not to reveal what we are working on, or what technology we are 
using, before products are announced.  I ssume you can understand.



--- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@y...> 
wrote:
> 
> Hello, 
> 
> You are right that the value for typical changed and unfortunately
> both values did not hit the mark that we saw on the bench. While 30 
mA
> was too low, 60 is too high. 
> 
> Acceptance criteria for test is 70 mAs max, this includes temp
> variation and chip-to-chip variations. So consider 70 mAs the max
> value. Test is done with peripherals enabled, that means, the clock 
is
> provided to most of the flipflops, which causes the current
> consumption. Running the peripherals or just having them enabled 
does
> not show a difference in power consumption of more than 5 mAs. In
> fact, running them caused the current to drop a couple mAs. The
> highest current we measured in characterization based on a core
> voltage of 1.8V was less than 60 mAs, only if the core voltage
> increases to the max. of 1.95V we saw single devices exceeding 60 
mAs. 
> 
> When we really disabled the peripherals using the PCONP register and
> leaving the VPB-divider at the initial divide by 4, we saw current
> consumption around 35 mAs running at 60 MHz without peripherals. 
> 
> The major difference is disabling the peripherals and / or the VPD
> divider for the peripheral bus. With the divider you can save 
approx.
> 10 mAs and with disabling them all approx. 15 mAs based on 60 MHz
> operation.
> 
> There are so many conditions but in general, the active power is
> highly dependend on your core voltage, highly dependend on your
> VPD-DIV, highly dependend on the settings in PCONP, MAM-enabled, PLL
> enabled.
> Less dependency but still some differences for single peripherals
> running or not, operating temperature.
> 
> Idle power depends mostly on the frequency provided to the
> peripherals, so VPBDIV and PCONP. Disabling the PLL also makes a
> significant difference. Recommendation disable PLL and set VPBDIV 
to 4
> while disableing unused peripherals in PCONP. Measured value used
> above recommendations at 10 MHz and all peripherals disabled was 2.3
> mAs, same conditions 20 MHz was 4.5 mAs. With PLL enabled and 
running
> the peripherals at max speed idel power can be around 20 mAs.
> 
> For power down current the most important factor is temperature! 
While
> most of our devices are around 10 uAs at room temp, they are >100 
uAs
> at 85C.
> 
> Let me apologize for the confusion. Will work hard to do better in 
the
> future!
> 
> btw. as a courtesy it would be nice to identify yourself by name. 
> 
> Robert
> 
> 
> --- In lpc2000@yahoogroups.com, "lp2000c" <lp2000c@e...> wrote:
> > 
> > The latest LPC2114 Data Sheet shows a Typical 1.8V current of 60 
mA 
> > (at 25 degrees, with no active peripherals).  This is double the 
> > value published in the previous "prleiminary" revision.
> > 
> > Philips Apss:
> > What is the Maximum current draw (including chip-to-chip 
variations, 
> > and temperature efffects?)
> > What is current draw with all peripherals active?

I finally got to the point of shutting down the LPC2138 on the Keil 
development board. Battery life is critical to my application, 
therefore I need to verify the sleep specification. At room 
temperature, with all I/O configured as input except for JTAG, I am 
measuring 350mA just on the VDD pins! Far from 10uA. All peripheral 
clocks are disabled except the RTC which is configured to use the 
32kHz. 

FYI:
Vbat: ~31uA while processor is on, ~18uA during powerdown. (Just for 
the RTC?!?!)

When it comes to sleep current issues, the first thing vendors 
usually question is the I/O state. The following are the relevant 
register values:

PINSEL0: 0x0
PINSEL1: 0x0
PINSEL2: 0x4

IODIR0: 0x0
IODIR1: 0x0

IOPIN0: 0x7EFFF7F8
IOPIN1: 0x03FF0000

I'm puzzled about the I/O:
1.) The IOPIN register does not necessarily reflect the state of the 
I/O line. For example, P0.4 is not connected on the Keil board. 
Since this pin is configured as an input, I would suspect the 
voltage on the pin to reflect the internal pullup, but it measures 
0V. Even more puzzling, IOPIN0 states this input is high. Go figure.

2.) Another concern: P0.31 is not connected, but configured as an 
input. If I measure the pin voltage it is 2.3 instead of 3.3V. This 
is also true for P1.16-23 and P1.24-25. Could I be leaking current 
through the pullup resistor?

-Tim



--- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@y...> 
wrote:
> 
> Hello, 
> 
> You are right that the value for typical changed and unfortunately
> both values did not hit the mark that we saw on the bench. While 
30 mA
> was too low, 60 is too high. 
> 
> Acceptance criteria for test is 70 mAs max, this includes temp
> variation and chip-to-chip variations. So consider 70 mAs the max
> value. Test is done with peripherals enabled, that means, the 
clock is
> provided to most of the flipflops, which causes the current
> consumption. Running the peripherals or just having them enabled 
does
> not show a difference in power consumption of more than 5 mAs. In
> fact, running them caused the current to drop a couple mAs. The
> highest current we measured in characterization based on a core
> voltage of 1.8V was less than 60 mAs, only if the core voltage
> increases to the max. of 1.95V we saw single devices exceeding 60 
mAs. 
> 
> When we really disabled the peripherals using the PCONP register 
and
> leaving the VPB-divider at the initial divide by 4, we saw current
> consumption around 35 mAs running at 60 MHz without peripherals. 
> 
> The major difference is disabling the peripherals and / or the VPD
> divider for the peripheral bus. With the divider you can save 
approx.
> 10 mAs and with disabling them all approx. 15 mAs based on 60 MHz
> operation.
> 
> There are so many conditions but in general, the active power is
> highly dependend on your core voltage, highly dependend on your
> VPD-DIV, highly dependend on the settings in PCONP, MAM-enabled, 
PLL
> enabled.
> Less dependency but still some differences for single peripherals
> running or not, operating temperature.
> 
> Idle power depends mostly on the frequency provided to the
> peripherals, so VPBDIV and PCONP. Disabling the PLL also makes a
> significant difference. Recommendation disable PLL and set VPBDIV 
to 4
> while disableing unused peripherals in PCONP. Measured value used
> above recommendations at 10 MHz and all peripherals disabled was 
2.3
> mAs, same conditions 20 MHz was 4.5 mAs. With PLL enabled and 
running
> the peripherals at max speed idel power can be around 20 mAs.
> 
> For power down current the most important factor is temperature! 
While
> most of our devices are around 10 uAs at room temp, they are >100 
uAs
> at 85C.
> 
> Let me apologize for the confusion. Will work hard to do better in 
the
> future!
> 
> btw. as a courtesy it would be nice to identify yourself by name. 
> 
> Robert
> 
> 
> --- In lpc2000@yahoogroups.com, "lp2000c" <lp2000c@e...> wrote:
> > 
> > The latest LPC2114 Data Sheet shows a Typical 1.8V current of 60 
mA 
> > (at 25 degrees, with no active peripherals).  This is double the 
> > value published in the previous "prleiminary" revision.
> > 
> > Philips Apss:
> > What is the Maximum current draw (including chip-to-chip 
variations, 
> > and temperature efffects?)
> > What is current draw with all peripherals active?

Tim,

I guess the 350 mA (the "m" should be a "u")was a typo. What you
measured in power down for the RTC is correct between 15 and 20 uAs. 
Logic in this process needs to run at 1.8V +/- 10 %. A pin like Vbat
needs a wider spec and a different voltage. The spec for Vbat will be
significantly extended to probably 2.0V-3.6V (characterization is
ongoing). To not damage the logic we need to convert the external
voltage down to 1.8V The converter uses most of the 18 uAs you measured. 
The higher current during active mode is due to an chip failure on the
first devices, which have been used to build evaluation boards. New
devices will not draw higher current during active mode on Vbat but
still draw the 15-20 uAs.

THIS INFORMATION IS SPECIFIC FOR THE LPC2130 series
Power down current on the first devices was measured around 140 uAs,
keeping all the RAM intact. Our latest lot with some fixes brings this
value down to approx 50 uAs. 
While this value might be too high for some of you, it might be good
enough for others and it is for sure a lot better than the previous
option to go into idle mode using the RTC.

Comparing an ARM build in 0.18um process to an AVR, PIC, MSP430 or you
name them is really comparing apples to oranges. New processes enable
the chip vendors to put more memory and build faster devices but the
leakage goes up. 

In the end the only thing I can tell you, this is as good as it gets
right now. Will let everybody know if we find ways to improve the
power down behavior. Keep in mind that active current is as low or
lower than an 8-bit running at the same clock rate delivering a lot
less performance. 

Regards, Robert

--- In lpc2000@yahoogroups.com, "tah2k" <tah2k@y...> wrote:
> 
> I finally got to the point of shutting down the LPC2138 on the Keil 
> development board. Battery life is critical to my application, 
> therefore I need to verify the sleep specification. At room 
> temperature, with all I/O configured as input except for JTAG, I am 
> measuring 350mA just on the VDD pins! Far from 10uA. All peripheral 
> clocks are disabled except the RTC which is configured to use the 
> 32kHz. 
> 
> FYI:
> Vbat: ~31uA while processor is on, ~18uA during powerdown. (Just for 
> the RTC?!?!)
> 
> When it comes to sleep current issues, the first thing vendors 
> usually question is the I/O state. The following are the relevant 
> register values:
> 
> PINSEL0: 0x0
> PINSEL1: 0x0
> PINSEL2: 0x4
> 
> IODIR0: 0x0
> IODIR1: 0x0
> 
> IOPIN0: 0x7EFFF7F8
> IOPIN1: 0x03FF0000
> 
> I'm puzzled about the I/O:
> 1.) The IOPIN register does not necessarily reflect the state of the 
> I/O line. For example, P0.4 is not connected on the Keil board. 
> Since this pin is configured as an input, I would suspect the 
> voltage on the pin to reflect the internal pullup, but it measures 
> 0V. Even more puzzling, IOPIN0 states this input is high. Go figure.
> 
> 2.) Another concern: P0.31 is not connected, but configured as an 
> input. If I measure the pin voltage it is 2.3 instead of 3.3V. This 
> is also true for P1.16-23 and P1.24-25. Could I be leaking current 
> through the pullup resistor?
> 
> -Tim
---  snip   -----

I didn't see an explanantion for the 350uA sleep current or my 
questions 1 and 2 concerning the I/O. Do I need to try a new device 
on the evaluation board?

50uA sleep current is perfect, 140uA is tolerable, and 350uA is a 
show stopper.

--- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@y...> 
wrote:
> 
> Tim,
> 
> I guess the 350 mA (the "m" should be a "u")was a typo. What you
> measured in power down for the RTC is correct between 15 and 20 
uAs. 
> Logic in this process needs to run at 1.8V +/- 10 %. A pin like 
Vbat
> needs a wider spec and a different voltage. The spec for Vbat will 
be
> significantly extended to probably 2.0V-3.6V (characterization is
> ongoing). To not damage the logic we need to convert the external
> voltage down to 1.8V The converter uses most of the 18 uAs you 
measured. 
> The higher current during active mode is due to an chip failure on 
the
> first devices, which have been used to build evaluation boards. New
> devices will not draw higher current during active mode on Vbat but
> still draw the 15-20 uAs.
> 
> THIS INFORMATION IS SPECIFIC FOR THE LPC2130 series
> Power down current on the first devices was measured around 140 
uAs,
> keeping all the RAM intact. Our latest lot with some fixes brings 
this
> value down to approx 50 uAs. 
> While this value might be too high for some of you, it might be 
good
> enough for others and it is for sure a lot better than the previous
> option to go into idle mode using the RTC.
> 
> Comparing an ARM build in 0.18um process to an AVR, PIC, MSP430 or 
you
> name them is really comparing apples to oranges. New processes 
enable
> the chip vendors to put more memory and build faster devices but 
the
> leakage goes up. 
> 
> In the end the only thing I can tell you, this is as good as it 
gets
> right now. Will let everybody know if we find ways to improve the
> power down behavior. Keep in mind that active current is as low or
> lower than an 8-bit running at the same clock rate delivering a lot
> less performance. 
> 
> Regards, Robert
> 
> --- In lpc2000@yahoogroups.com, "tah2k" <tah2k@y...> wrote:
> > 
> > I finally got to the point of shutting down the LPC2138 on the 
Keil 
> > development board. Battery life is critical to my application, 
> > therefore I need to verify the sleep specification. At room 
> > temperature, with all I/O configured as input except for JTAG, I 
am 
> > measuring 350mA just on the VDD pins! Far from 10uA. All 
peripheral 
> > clocks are disabled except the RTC which is configured to use 
the 
> > 32kHz. 
> > 
> > FYI:
> > Vbat: ~31uA while processor is on, ~18uA during powerdown. (Just 
for 
> > the RTC?!?!)
> > 
> > When it comes to sleep current issues, the first thing vendors 
> > usually question is the I/O state. The following are the 
relevant 
> > register values:
> > 
> > PINSEL0: 0x0
> > PINSEL1: 0x0
> > PINSEL2: 0x4
> > 
> > IODIR0: 0x0
> > IODIR1: 0x0
> > 
> > IOPIN0: 0x7EFFF7F8
> > IOPIN1: 0x03FF0000
> > 
> > I'm puzzled about the I/O:
> > 1.) The IOPIN register does not necessarily reflect the state of 
the 
> > I/O line. For example, P0.4 is not connected on the Keil board. 
> > Since this pin is configured as an input, I would suspect the 
> > voltage on the pin to reflect the internal pullup, but it 
measures 
> > 0V. Even more puzzling, IOPIN0 states this input is high. Go 
figure.
> > 
> > 2.) Another concern: P0.31 is not connected, but configured as 
an 
> > input. If I measure the pin voltage it is 2.3 instead of 3.3V. 
This 
> > is also true for P1.16-23 and P1.24-25. Could I be leaking 
current 

> > through the pullup resistor?
> > 
> > -Tim
> ---  snip   -----

--- In lpc2000@yahoogroups.com, "tah2k" <tah2k@y...> wrote:
> > > I'm puzzled about the I/O:
> > > 1.) The IOPIN register does not necessarily reflect the state 
of 
> the 
> > > I/O line. For example, P0.4 is not connected on the Keil board. 
> > > Since this pin is configured as an input, I would suspect the 
> > > voltage on the pin to reflect the internal pullup, but it 
> measures 
> > > 0V. Even more puzzling, IOPIN0 states this input is high. Go 
> figure.
> > > 

Which pullup is that?  AFAIK, P0 pins do not have internal pullups - 
should not be left as unconnected inputs.

> > > 2.) Another concern: P0.31 is not connected, but configured as 
> an 
> > > input. If I measure the pin voltage it is 2.3 instead of 3.3V. 

Data Sheet says that P0.31 is output only.  I don't know what happens 
if you set it as an input in the IODIR register, but I guess you 
shouldn't do that.

Philips Apps: Description of IODIR register should probably note 
that, especially since current description says "Bit 31 in IO0DIR
controls P0.31"

> This 
> > > is also true for P1.16-23 and P1.24-25. Could I be leaking 
> current 
> > > through the pullup resistor?

What is input impedence of device you are using to measure?  Note 
that pull-up current is only 15uA minimum (equivalent to 220K @ 3.3V).

> > > 
> > > -Tim
> > ---  snip   -----

--- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@y...> 
wrote:
> 
> The higher current during active mode is due to an chip failure on 
the
> first devices, which have been used to build evaluation boards. New
> devices will not draw higher current during active mode on Vbat but
> still draw the 15-20 uAs.
> 
> THIS INFORMATION IS SPECIFIC FOR THE LPC2130 series
> Power down current on the first devices was measured around 140 uAs,
> keeping all the RAM intact. Our latest lot with some fixes brings 
this
> value down to approx 50 uAs. 

How can one tell whether a given chip is one of the "first devices" 
or "latest lot"?  Was the device rev bumped up? Can we tell by date 
code?

Any ETA on an errata sheet for these devices?

The first digit subsequent to the date code will be either a "-
", "A", or "B", indicating the revision of the chip.

--- In lpc2000@yahoogroups.com, "lp2000c" <lp2000c@e...> wrote:
>
> 
> --- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@y...> 
> wrote:
> > 
> > The higher current during active mode is due to an chip failure 
on 
> the
> > first devices, which have been used to build evaluation boards. 
New
> > devices will not draw higher current during active mode on Vbat 
but
> > still draw the 15-20 uAs.
> > 
> > THIS INFORMATION IS SPECIFIC FOR THE LPC2130 series
> > Power down current on the first devices was measured around 140 
uAs,
> > keeping all the RAM intact. Our latest lot with some fixes 
brings 
> this
> > value down to approx 50 uAs. 
> 
> How can one tell whether a given chip is one of the "first 
devices" 
> or "latest lot"?  Was the device rev bumped up? Can we tell by 
date 

> code?
> 
> Any ETA on an errata sheet for these devices?
>