Odd Timer Behaviour
2004-01-20 by Robert Adsett
I've just run into some odd timer behaviour while working on timing
routines. I'm going to spend some more time nailing down a good
demonstration but I thought I would report my preliminary results and see
what ideas anyone might have.
I'm using one of the match register against T0 to measure a time
period. Basically load the match with current count plus whatever count I
want to wait for and then wait for the timer HW to trigger a match. When I
went to measure it I found a discrete jump in the error I was getting at
around 26 uS. Delving further I found the time it was taking in counts
wasn't matching what I was asking for. For from about 11uS to 25 uS I get
an error of 1 or maybe 2 counts. (quite reasonable for the 10MHz frequency
I'm using), also the error may be positive or negative. At 26 uS (260
counts) I suddenly see a wait of at least 268 counts or a consistent
positive error of 8. Checking further I find period increments in the
error at logarithmic time intervals (some sort of bit ripple effect?). The
table below shows what I mean. The first column is the request wait in
uS. The second is the excess wait produced in counts.
Request Wait, Excess Counts
20, 0
26, 9
450, 19
6700,28
20100,37
105500,44
The worst case from my view is at the 26uS point where this results in a 3%
or so error. After that the error decreases (on a percentage basis).
Robert
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