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Bizarre interaction between T1MR0 INTs and UART0's Baudrate

Bizarre interaction between T1MR0 INTs and UART0's Baudrate

2004-02-01 by microbit

This is a weird one, I've reduced the functions to the ones that seem to
interfere with one another :
(on LPC2106, clocked at 10 MHz, on Nohau tester board)
I initialise T1 to Reset and Interrupt on Match(0) every 1 mS.
(T1PR=2, T1MR0=5000, T1MCR=3)
Works 100% alone or mixed with other functions.
I initialise UART0 to run at 19200 Bps RX and TX Interrupts.
(Or even polled with just a single char TXd, no INTs).
Works 100% alone or mixed with other functions.
When running T1MR0 Interrupt **AND** UART0 at 19,200 Bps things go ape :
-------------------------------------------------------------------------------------------
- After Cold reset, T1MR0 Interrupt now ticks 6 TIMES SLOWER,
and the Baud rate is correct providing I have P0.15 and P0.14 jumpers
to LEDS in place.
(If P0.14 and P0.15 are floating - no jumpers - then the Timer is correct but
;baudrate is too fast)
- If the same program is executed from RAM, and it is started with the P0.14
and P0.15 jumpers installed, the Timer Interrupt now ticks correctly but my Baudrate
is suddenly 6 times faster (1 bit time for 19,200 is only 17.06687 uS)
????
VPBDIV is left at its default so pclk = cclk/4.
I've changed around slots on the VIC, swapped priorities between the 2 but it's not there.
The same syndrome occurs when the UART INTs are disabled, and I just TX 0x55 continuously
with polling on U0LSR.
Has anyone seen anything like this ???
B regards,
Kris

Re: [lpc2100] Bizarre interaction between T1MR0 INTs and UART0's Baudrate

2004-02-01 by microbit

I thought I'd have the courtesy of indicating that the
obvious of course has transpired here in the interim :

I hadn't used the IAP yet, and of course P0.14 determines
whether the Bootloader is called on Reset :-(

I also overlooked that the prescaler PR's value causes a division
of PR+1.

All runs like a treat now of course !
Bah.

-- Kris

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