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A couple questions on Software Interrupts

A couple questions on Software Interrupts

2005-03-01 by Leighton Rowe

I haven't played around swi's much but most (if not all) swi_handler 
examples that I've seen were written in straight assembly language 
(some even containing "swi" instructions).

However from lpc User Manual, I noticed that 2 registers VICSoftInt 
& VICSoftIntClear are used to force software interrupts.

How different will the swi_handler be should I use the 2 SoftInt 
Registers available? 

Would I be able to use a c-style case structure on VICSoftIntClear?

thanks in advance,
Leighton



However,  and looking through ARM7 Programming guides, there seems 
to be multiple ways of my I'm picking up two ways in which From the 
User Manual

Re: [lpc2000] A couple questions on Software Interrupts

2005-03-01 by Robert Adsett

At 07:36 PM 3/1/05 +0000, Leighton Rowe wrote:
>I haven't played around swi's much but most (if not all) swi_handler
>examples that I've seen were written in straight assembly language
>(some even containing "swi" instructions).
>
>However from lpc User Manual, I noticed that 2 registers VICSoftInt
>& VICSoftIntClear are used to force software interrupts.

I think you are confusing two different things.  The SWI op-code generates 
an exception to the SWI exception handler not the irq exception 
handler.  VICSoftInt is used to generate an IRQ exception which is a 
different beast and will end up being vectored through the VIC as the HW 
interrupts are.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

Re: A couple questions on Software Interrupts

2005-03-01 by Leighton Rowe

> I think you are confusing two different things.  The SWI op-code 
generates 
> an exception to the SWI exception handler not the irq exception 
> handler.  VICSoftInt is used to generate an IRQ exception which is 
a 
> different beast and will end up being vectored through the VIC as 
the HW 
> interrupts are.
> 
> Robert

Oh ok. Didn't realize setting "VICSoftInt" bits actually 
forces "IRQ "exceptions. It makes the whole concept a bit confusing, 
but I get the idea. Thanks for the clarification.

Leighton

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