Lpc2000

Hi,

I'm "playing" with interrupts.
Now I have this situation:

Within the VIC some Interrupts are enabled and set.
The ARM7 Core is in Usermode, the I Flag is 0.

Now I miss my Interrupt generation.

What could be wrong?

Before this situation, for example I clear the Interrupts on the 
VIC with 

    /* disable all Interrupts on the VIC unit */
    LPC21_VIC_INT_ENCLR = 0xFFFFFFFFul;
    /* reset current interrupt Flags */
    LPC21_VIC_SOFTINT_CLR = 0xFFFFFFFFul;

Later I generate a SWI. Within the Software Interrupt function I 
call this function:

void fl_destroyAppl(void) __arm 
{
    /* disable IRQ, FIRQ (Mode_SVC|I_Bit|F_Bit) */
    __asm { 
		MSR CPSR_c, #0xD3 	/* (Mode_SVC|I_Bit|F_Bit) */
                LDR     R0, =0xE01FC040 /* MEMMAP */
                MOV     R1, #1 	/* User Flash Mode */
                STR     R1, [R0]
    };

    ((void(*)(void))0)();
}


On address 0 the program restarts and the startup initializes and 
enables the interrupts. But now the Interrupt engine is wrong.

Do you have a better command to reset the CPU? I want also reset 
the internal resources. But I didn't find a Software Reset.

Thank you.
-- 
Steffen Rose

Have you tried using the Watchdog Timer to reset?  
On other projects I've noticed that just jumping to address 0 can leave
the processor in a strange state (it's not really resetting the
processor), and subsequent interrupts were ignored until we hit the reset
button.  If you have a Watchdog Timer, that may work better to reset the
processor state.  Just set the timeout value to something small, but long
enough to execute the next few instructions (so you can clean up stuff and
enter an infinite loop)

Jim

--- Steffen Rose <ro@...> wrote:

> Hi,
> 
> I'm "playing" with interrupts.
> Now I have this situation:
> 
> Within the VIC some Interrupts are enabled and set.
> The ARM7 Core is in Usermode, the I Flag is 0.
> 
> Now I miss my Interrupt generation.
> 
> What could be wrong?
> 
> Before this situation, for example I clear the Interrupts on the 
> VIC with 
> 
>     /* disable all Interrupts on the VIC unit */
>     LPC21_VIC_INT_ENCLR = 0xFFFFFFFFul;
>     /* reset current interrupt Flags */
>     LPC21_VIC_SOFTINT_CLR = 0xFFFFFFFFul;
> 
> Later I generate a SWI. Within the Software Interrupt function I 
> call this function:
> 
> void fl_destroyAppl(void) __arm 
> {
>     /* disable IRQ, FIRQ (Mode_SVC|I_Bit|F_Bit) */
>     __asm { 
> 		MSR CPSR_c, #0xD3 	/* (Mode_SVC|I_Bit|F_Bit) */
>                 LDR     R0, =0xE01FC040 /* MEMMAP */
>                 MOV     R1, #1 	/* User Flash Mode */
>                 STR     R1, [R0]
>     };
> 
>     ((void(*)(void))0)();
> }
> 
> 
> On address 0 the program restarts and the startup initializes and 
> enables the interrupts. But now the Interrupt engine is wrong.
> 
> Do you have a better command to reset the CPU? I want also reset 
> the internal resources. But I didn't find a Software Reset.
> 
> Thank you.
> -- 
> Steffen Rose
> 


----------------------------------------------------------
Jim Parziale
Email: nuncio_bitis@...
Malden, MA
----------------------------------------------------------


		
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Hi Jim,

On Thursday 02 June 2005 19:03, Jim Parziale wrote:
> Have you tried using the Watchdog Timer to reset?

Thank you for this hint. Now it works.

But, what can I do, if the Watchdog is configured to generate 
IRQ's? Can I change it to Reset-Generation?

-- 
Steffen Rose

Hmmm... where the WDT is and to what signal it's attached in the processor
could be hardware dependent.  If the watchdog isn't attached to the
processor reset, I don't know what then.  Is there another way you could
reset the processor from software?  I've never seen a watchdog timeout
*not* reset the processor.

--- Steffen Rose <ro@...> wrote:

> Hi Jim,
> 
> On Thursday 02 June 2005 19:03, Jim Parziale wrote:
> > Have you tried using the Watchdog Timer to reset?
> 
> Thank you for this hint. Now it works.
> 
> But, what can I do, if the Watchdog is configured to generate 
> IRQ's? Can I change it to Reset-Generation?
> 
> -- 
> Steffen Rose
> 


----------------------------------------------------------
Jim Parziale
Email: nuncio_bitis@...
Malden, MA
----------------------------------------------------------


		
__________________________________ 
Discover Yahoo! 
Find restaurants, movies, travel and more fun for the weekend. Check it out! 
http://discover.yahoo.com/weekend.html

Hi,

On Friday 03 June 2005 15:21, Jim Parziale wrote:
> Hmmm... where the WDT is and to what signal it's attached in
> the processor could be hardware dependent.  If the watchdog
> isn't attached to the processor reset, I don't know what then.
>  Is there another way you could reset the processor from
> software?  I've never seen a watchdog timeout *not* reset the
> processor.

On the Philips ARM it is possible to configure for Reset or for 
IRQ generation by software.

> > But, what can I do, if the Watchdog is configured to
> > generate IRQ's? Can I change it to Reset-Generation?

I don't find information, which parts of the watchdog are 
protected after it is enabled.

-- 
Steffen Rose

> On the Philips ARM it is possible to configure for Reset or for 
> IRQ generation by software.

Just for the purpose of resetting, couldn't you configure the WDT for
reset?  Then in your startup code you must already set it for IRQ.  That
wuold definitely work out well for you.



----------------------------------------------------------
Jim Parziale
Email: nuncio_bitis@...
Malden, MA
----------------------------------------------------------

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