Lpc2000

Hi,

to protect a shared data area against simultanous access by an 
interrupt
routine and a main task, I'm using the VICIntEnClear / VICIntEnable
registers. I intentionally don't wanna disable all the interrupts 
because
this would cause too much latency for other interrupts.
However, due to the pipelined instructions, one cannot guarantee that 
no
interrupt occures just after it was disabled by a write to the 
VICIntEnClear
register.
I suppose that I can place a few dummy instructions right after the
instruction that writes the VICIntEnClear register to prevent 
simultanous
access but I'm not sure how many clock cycles this delay must be. The
technical manual of the PrimeCell Vectored Interruptcontroller 
mentions a
worst case scenario of 13 cycles ( Interrupt synchronization + Worst 
case
Interrupt disabling period).
Anyone who can confirm this?

Best regards,

Patrick Smout

--- In lpc2000@yahoogroups.com, "smoutpatrick" <sonpat@b...> wrote:
> Hi,
> 
> to protect a shared data area against simultanous access by an 
> interrupt routine and a main task, I'm using the VICIntEnClear / 
> VICIntEnable registers. I intentionally don't wanna disable all the 
> interrupts because this would cause too much latency for other 
> interrupts.
> However, due to the pipelined instructions, one cannot guarantee
> that no interrupt occures just after it was disabled by a write to 
> the VICIntEnClear register.
> I suppose that I can place a few dummy instructions right after the
> instruction that writes the VICIntEnClear register to prevent 
> simultanous access but I'm not sure how many clock cycles this 
> delay must be.
> The technical manual of the PrimeCell Vectored Interruptcontroller 
> mentions a worst case scenario of 13 cycles ( Interrupt 
> synchronization + Worst case Interrupt disabling period).
> Anyone who can confirm this?

If all the "other interrupts" can use the same priority, you can make 
them FIQ, and only disable the IRQs through MSR CPSR_C, #xx.  This is 
much faster.

Karl Olsen