68300

From: Robert Manktelow [mailto:robert.manktelow@...]
> 
> I have had no responses to this posting. The original is 
> included below.
> Here is an update which I think is helpful.
> 
> We replaced our 6.5536MHz clock source, with a signal 
> generator, and ran the code whilst ramping up the frequency
> from 2 MHz.
> Up to just over 4 MHz the interrupt rate increased in line 
> with the signal generator frequency but beyond this it started
> to decrease to a minimum in a random fashion.
> 
> Conclusion - the MAXIMUM PCLK frequency = the 68331 system clock % 4.

...if you have a look at chapter 7.5.6 "Auxiliary Timer Clock Input (PCLK)"
of the 331 UM, you'll find:
"... PCLK has hysteresis. Any pulse longer than two system clocks is
guaranteed
to be valid and any pulse shorter than one system clock is ignored..."

Since there are least 2 clocks needed for recognition (of each state
high/low?), one could derive that clock/4 from there as well.

Stefan