68300

Hello All

I have had no responses to this posting. The original is included below.
Here is an update which I think is helpful.

We replaced our 6.5536MHz clock source, with a signal generator, and ran the
code whilst ramping up the frequency from 2 MHz.
Up to just over 4 MHz the interrupt rate increased in line with the signal
generator frequency but beyond this it started to decrease to a minimum in a
random fashion.

Conclusion - the MAXIMUM PCLK frequency = the 68331 system clock % 4.
Is this correct or am I doing something wrong.

It would help me enormously to receive confirmation of this conclusion so I
know whether to change the hardware to use another method

----------------------------------------------------------------------------
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I am feeding a 6.5536 MHz clock (50:50 mark/space ratio) into the PCLK pin
of
the GPT and using the 16 bit free running TCNT counter to produce a 100 Hz
interrupts.
This does not work using a 16.667 MHz system clock.

Replacing PCLK with the system clock divided by 4 (TMSK2 register bits
CPR[]=000) works but of course the interrupt rate is wrong.
I suspect the synchroniser & digital filter (Figure 7-2 of the Users Manual)
may be filtering out the clock coming into PCLK but am unsure.

Can anybody confirm my suspicions or tell me what is the maximum frequency I
can feed into PCLK with a 16.667 MHz system clock please. PS I must have an
accurate 100 Hz interrupt as the RTOS derives its time and date from this.

-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346

Most of the signal inputs on the 6800 and 68K family are limited to Fs/4 because that is the internally distributed frequency in the SCIM.  

One exception is that the TPU-2 and above have a provision for clocking at Fs/2.

I haven't had time to read through the ('375) manual to verify, but this was the case on the 68HC916 series.

I generate such signals using the PIT and using Fs/4/N

;------------------------------------------------------------------------
; SCIM2E configuration includes stopping watchdog,
; setting PIT to 100 ticks/second and exposing E4 as DS*
; The rest of SCIM2E is as defaulted -- ports as inputs.

        move.w #$F07F,(SCIMMCR,A0)    ; disable unused outputs
        clr.w  (SYPCR,A0)             ; disable watchdog timer for now
        move.w #$01A3,(PITR,A0)       ; 100 ticks per second at 33.3 MHz
        move.w #$0340,(PICR,A0)       ; level 3, vector 64, address $0100
        move.b #$10,(PEPAR,A0)        ; E4 is ds* for BDM

To get 100 time slices per second at 16.667 use 0x00D1 or 0x00D2 in PITR


[Non-text portions of this message have been removed]

From: Robert Manktelow [mailto:robert.manktelow@...]
> 
> I have had no responses to this posting. The original is 
> included below.
> Here is an update which I think is helpful.
> 
> We replaced our 6.5536MHz clock source, with a signal 
> generator, and ran the code whilst ramping up the frequency
> from 2 MHz.
> Up to just over 4 MHz the interrupt rate increased in line 
> with the signal generator frequency but beyond this it started
> to decrease to a minimum in a random fashion.
> 
> Conclusion - the MAXIMUM PCLK frequency = the 68331 system clock % 4.

...if you have a look at chapter 7.5.6 "Auxiliary Timer Clock Input (PCLK)"
of the 331 UM, you'll find:
"... PCLK has hysteresis. Any pulse longer than two system clocks is
guaranteed
to be valid and any pulse shorter than one system clock is ignored..."

Since there are least 2 clocks needed for recognition (of each state
high/low?), one could derive that clock/4 from there as well.

Stefan