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Re: [68300] 68331 PCLK frequency - an update

2002-08-29 by Jeff Andle

Most of the signal inputs on the 6800 and 68K family are limited to Fs/4 because that is the internally distributed frequency in the SCIM.  

One exception is that the TPU-2 and above have a provision for clocking at Fs/2.

I haven't had time to read through the ('375) manual to verify, but this was the case on the 68HC916 series.

I generate such signals using the PIT and using Fs/4/N

;------------------------------------------------------------------------
; SCIM2E configuration includes stopping watchdog,
; setting PIT to 100 ticks/second and exposing E4 as DS*
; The rest of SCIM2E is as defaulted -- ports as inputs.

        move.w #$F07F,(SCIMMCR,A0)    ; disable unused outputs
        clr.w  (SYPCR,A0)             ; disable watchdog timer for now
        move.w #$01A3,(PITR,A0)       ; 100 ticks per second at 33.3 MHz
        move.w #$0340,(PICR,A0)       ; level 3, vector 64, address $0100
        move.b #$10,(PEPAR,A0)        ; E4 is ds* for BDM

To get 100 time slices per second at 16.667 use 0x00D1 or 0x00D2 in PITR


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