68300

Hello All

I have had no responses to this posting. The original is included below.
Here is an update which I think is helpful.

We replaced our 6.5536MHz clock source, with a signal generator, and ran the
code whilst ramping up the frequency from 2 MHz.
Up to just over 4 MHz the interrupt rate increased in line with the signal
generator frequency but beyond this it started to decrease to a minimum in a
random fashion.

Conclusion - the MAXIMUM PCLK frequency = the 68331 system clock % 4.
Is this correct or am I doing something wrong.

It would help me enormously to receive confirmation of this conclusion so I
know whether to change the hardware to use another method

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I am feeding a 6.5536 MHz clock (50:50 mark/space ratio) into the PCLK pin
of
the GPT and using the 16 bit free running TCNT counter to produce a 100 Hz
interrupts.
This does not work using a 16.667 MHz system clock.

Replacing PCLK with the system clock divided by 4 (TMSK2 register bits
CPR[]=000) works but of course the interrupt rate is wrong.
I suspect the synchroniser & digital filter (Figure 7-2 of the Users Manual)
may be filtering out the clock coming into PCLK but am unsure.

Can anybody confirm my suspicions or tell me what is the maximum frequency I
can feed into PCLK with a 16.667 MHz system clock please. PS I must have an
accurate 100 Hz interrupt as the RTOS derives its time and date from this.

-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346