68300

Jeff,

Look for answers below in text.

Regards,

Charlie
  ----- Original Message ----- 
  From: Jeff 
  To: 68300@yahoogroups.com 
  Sent: Thursday, September 12, 2002 12:09 PM
  Subject: [68300] Re: dead (?) CPU -- RESET not released


  I have built prototype boards with TSC pulled low as indicated in the 
  attached e-mail (with Motorola tech support).

  The chips will NOT release reset (it stays low).
  All of the pins that I have connected appear tristated, but in single 

  chip mode this is to be expected...
  *************************************************************************************
  If you have modclk tied low, you will not be using the VCO / PLL.  So, the chip will run at what ever frequency you are driving into EXTAL.  If you have no clock, you will never release reset.
  ******************************************************************************************


  I have the CPU configured as follows:
  66.667MHz 45/55 duty cycle oscillator chip giving a clean 2X clock 
  signal on a short lead.  I did not pin out CLKOUT so I have no access 
  to this as a diagnostic.

  ***********************************************************************************************************************
  You really need clock out to initially check out your system.  This will tell you whether your clocking scheme is working.
  ***************************************************************************************************************************

  MODCLK is hard wired low.
  BERR is tied low (single chip mode) -- first I used 10K and now it is 
  hard wire low...

  *******************************************************************************************************************************
  You can hard wire BERR low but you will not be able to use external interrupts.  Yes, I know that the manual says you can tie BERR low if you are using the Single Chip mode.  However, all external interrupts will be treated as "Spurious Interrupts".  We won't mention any names about who left this little "funny aspect" of the part in the manual.  It has been corrected in the on-line version to say that you need to release BERR after the release of reset if you want to use external interrupts.
  ************************************************************************************************************************************

  HALT is tied high through 10K and is high
  BKPT is tied high through 4.7K and is high

  RST tied high through 1K but measures 60 mV... (will NOT release)

  BGACK and BR are tied together and the pair is tied high through a 
  10K resistor. 

  **************************************************************************
  NO NO NO NO H... NO.  BGACK is active from the release of reset even in the single chip mode and it will definitely screw up the BDM mode.  BGACK and BR are configured separately and you can get some strange goings-on.  Do not tie these pins together.  However, it is imperative that they both be pulled up.  This is probably not going to cause you any problems right now but it is horrible design practice and it will bite you sooner or later.
  ****************************************************************************** 

  NOTE that the BR & BGACK nodes are at 1.5V and do NOT appear to be 
  tristated.  When I remove the 10K pull-up they remain at 1.5V. 

  BR and BGACK should both be inputs... but the manual says they have B-
  type output drivers.

  Is it possible one of them is coming up as CSE or CS[0] and is 
  pulling the other low? 

  ************************
  YES.  BR and BGACK are configured separately.  BGACK is a really dangerous pin and it should never be left floating.
  *********************************************

  Regards,

  Charlie 





  > 
  > Dear Mr. Andle:
  > 
  > In reply to your Service Request SR 1-35542677 (see details below):
  > 
  > You are correct.  The 'F375 documentation has some errors in it.  
  The TSC pin needs be pulled low for normal operation and pulled to 
  Vdd for tristate operate.  Sorry for the incorrect information.  I 
  have asked the factory to update this information in the data book.
  > 
  > ************ Details of your request: ************
  > 
  > Date Opened :   7/11/2002 11:48:59 AM
  > Product :       MC68F375BGMZP33
  > Topic :         Technical Request
  > Subject:        68F375 erratta?  TSC
  > 
  > Description : 
  > 
  > page 4-69 says that asserting a logic low on TSC (I assume this 
  means VSS) places the MCU into high impedance mode.
  > 
  > Please confirm that TSC-->VSS ENABLES outputs.



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