68300

****************************************************************************
*********
  If you have modclk tied low, you will not be using the VCO / PLL.  So, the
chip will run at what ever frequency you are driving into EXTAL.  If you
have no clock, you will never release reset.

****************************************************************************
**************
** The documentation says that with MODCLK low I want 2Fsys...
** HOWEVER, when I removed the 66MHz oscillator
** (no mean feat removing a metal package SMT oscillator
** without even any solder braid!) and replayed it with the
** 16.78MHz SMT oscillator from my 68HC916Y3 version,
** it all works.  Definitely a clock problem but the 66MHz clock
** was very stable...

** The behavior suggests that the manual is in error and what you said is
correct --
** I need a 33 MHz external oscillator to operate at 33 MHz...



  I have the CPU configured as follows:
  66.667MHz 45/55 duty cycle oscillator chip giving a clean 2X clock
  signal on a short lead.  I did not pin out CLKOUT so I have no access
  to this as a diagnostic.

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*******************************************
  You really need clock out to initially check out your system.  This will
tell you whether your clocking scheme is working.

****************************************************************************
***********************************************
** there are a few pins I *wish* I had pinned out for diagnostic purposes...


****************************************************************************
***************************************************
  You can hard wire BERR low but you will not be able to use external
interrupts.  Yes, I know that the manual says you can tie BERR low if you
are using the Single Chip mode.  However, all external interrupts will be
treated as "Spurious Interrupts".  We won't mention any names about who left
this little "funny aspect" of the part in the manual.  It has been corrected
in the on-line version to say that you need to release BERR after the
release of reset if you want to use external interrupts.

****************************************************************************
********************************************************
** I don't (now), but I will take that under advisement (archive this
e-mail)
** in case i try that later and forget why it failed...


  BGACK and BR are tied together and the pair is tied high through a 10K
resistor.
  **************************************************************************
  NO NO NO NO H... NO.  BGACK is active from the release of reset even in
the single chip mode and it will definitely screw up the BDM mode.  BGACK
and BR are configured separately and you can get some strange goings-on.  Do
not tie these pins together.  However, it is imperative that they both be
pulled up.  This is probably not going to cause you any problems right now
but it is horrible design practice and it will bite you sooner or later.
 ***************************************************************************
** yeah, when I explained the possibility that one is CS[0]
** at startup and that I risked this to save a resistor he kicked me too...
** It will NOT be this way on the pilot production rev's.
** I assume the problems it can cause will all be random failure to start
up,
** NOT sudden failures once operating?
** BGACK and BR bit me on the initial HC916Y3 version of this sensor
controller as well.


  ************************
  YES.  BR and BGACK are configured separately.  BGACK is a really dangerous
pin and it should never be left floating.
  *********************************************
** I took a functional 916Y3 unit and shorted the nodes --
** there was no problem, but as you say, spurious, and that
** is a different integration module as well...
** mental note -- while the trace connecting them is under the chip,
** at least put the resistor back on!