68300

Robert,
 
I think from reading the prior emails, you probably understand that the SPI master DOES NOT KNOW when the slave has data ready.  You have to make up your own protocol.  Many schemes involve the processor just polling the slave SPI by sending a byte of "null" data and then looking at what the slave sent back.
 
Also, on a different topic, many people think that they should poll the SPIF flag to indicate when the last byte has been transmitted.  This is no a good thing to do.  The SPIF flag indicates that another byte can be written to the Transmit Data Register, NOT the transmit shifter.  So, as soon as the last byte of data is delivered from the Transmit Data Register to the Transmit Shifter, the SPIF flag sets.  However, the data is still shifting.  If the SPE bit is cleared by software, the byte being currently transmitted will get truncated.
 
So, the moral of this storey is that you should poll the SPE bit to determine when all activity from the SPI is completed.  (The bit self clears when the transmission is finished.)
 
Charlie

-----Original Message-----
From: Robert Manktelow [mailto:robert.manktelow@...]
Sent: Thursday, October 10, 2002 10:57 AM
To: Yahoo 68300 group
Subject: [68300] QSPI - Can it do this?


Hello All
This is a general question about SPI operation, and QSPI on the CPU32 in
particular.

The Set-up
The CPU32 is SPI master and there is one slave. As I understand it the CPU32
is therefore responsible for generating both the SPI clock and the chip
select for the slave throughout the transaction.

The transaction sequence is the CPU asks for information from the slave, by
sending two bytes to it, which define the request. Chip Select, SPI clock
and the DO are toggled by the CPU32 to achieve this - so far all is well.
The slave has to first decode the request and then respond by sending back a
number of bytes, dependant on the request sent.

My question is:-
How is the slave's response data transferred into the CPU32?
The problem I have is that the CPU32 does not know when the response data is
likely to start or how many bytes there are to be transferred.
Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
slave's chip active and drive the SPI clock during this "read" part of the
transaction.

Cheers
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346



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