68300

Hello All
This is a general question about SPI operation, and QSPI on the CPU32 in
particular.

The Set-up
The CPU32 is SPI master and there is one slave. As I understand it the CPU32
is therefore responsible for generating both the SPI clock and the chip
select for the slave throughout the transaction.

The transaction sequence is the CPU asks for information from the slave, by
sending two bytes to it, which define the request. Chip Select, SPI clock
and the DO are toggled by the CPU32 to achieve this - so far all is well.
The slave has to first decode the request and then respond by sending back a
number of bytes, dependant on the request sent.

My question is:-
How is the slave's response data transferred into the CPU32?
The problem I have is that the CPU32 does not know when the response data is
likely to start or how many bytes there are to be transferred.
Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
slave's chip active and drive the SPI clock during this "read" part of the
transaction.

Cheers
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346

Robert,

Your understanding of the master/slave relationship is correct.  The master
always generates the clock and the CS during any transaction.  Transactions
are full duplex, but usually the peripheral utilizes the SPI connection
only half duplex.  Like in your example, the transaction begins with two
8-bit transfers (or one 16-bit transfer if the peripheral is fast) where
only MOSI is meaningful.  The next N transfers use only MISO because you're
just reading data from the peripheral.  I've used some peripherals that
employ true full-duplex communication.  It got a little tricky at times.

SPI peripherals (ie, slaves) have specs for the required wait time between
sequential transfers while CS remains asserted.  This wait time allows the
peripheral to get ready for the next transfer, during which the peripheral
may have to provide data.  Good peripherals allow continuous transfers with
no wait time;  I guess they're just fast.  The CPU32 programs the QSPI with
the delay time (DTL in SPCR1) and other important factors.

As for the master determining the end of the transfer, the software on the
master must know what it is requesting and how many transfers' worth of
data to expect.  So the CPU32 *does* have to know how many bytes there are
to be transferred.  What's great about the QSPI is that you can simply set
up the entire transaction (multiple SPI transfers) all at once.  When it's
done, you'll have your data waiting in the QSPI Rx area.

Jeff





"Robert Manktelow" <robert.manktelow@...> on 10/10/2002 08:57:28
AM

Please respond to 68300@yahoogroups.com

To:    "Yahoo 68300 group" <68300@yahoogroups.com>
cc:

Subject:    [68300] QSPI - Can it do this?


Hello All
This is a general question about SPI operation, and QSPI on the CPU32 in
particular.

The Set-up
The CPU32 is SPI master and there is one slave. As I understand it the
CPU32
is therefore responsible for generating both the SPI clock and the chip
select for the slave throughout the transaction.

The transaction sequence is the CPU asks for information from the slave, by
sending two bytes to it, which define the request. Chip Select, SPI clock
and the DO are toggled by the CPU32 to achieve this - so far all is well.
The slave has to first decode the request and then respond by sending back
a
number of bytes, dependant on the request sent.

My question is:-
How is the slave's response data transferred into the CPU32?
The problem I have is that the CPU32 does not know when the response data
is
likely to start or how many bytes there are to be transferred.
Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
slave's chip active and drive the SPI clock during this "read" part of the
transaction.

Cheers
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346



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At 04:57 PM 10/10/2002 +0100, you wrote:
>Hello All
>This is a general question about SPI operation, and QSPI on the CPU32 in
>particular.


>My question is:-
>How is the slave's response data transferred into the CPU32?

As the data is being clocked out of the CPU32, the data from the slave is 
being clocked in to the CPU32. They happen at the same time.

>The problem I have is that the CPU32 does not know when the response data is
>likely to start or how many bytes there are to be transferred.
>Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
>slave's chip active and drive the SPI clock during this "read" part of the
>transaction.

You have to write yourself a protocol.
1) The master sends a request to the slave, the slave sends back idle words.
2) The master sends idle words, the slave sends a message indicating how 
many words are to follow.
3) The master sends idle words, one for each word in the message, the slave 
sends the requested data back to the master.
4) The master sends a thank you words, the slave sends an idle words.
5) The master sends an idle word, the slave sends a you're welcome word

The bigger problem comes in where the QSPI has a 16 word queue. It would be 
really convenient if the transactions were 16 words or less or else you 
have to buffer and reconstruct.

Andrei

>Cheers
>-
>Robert Manktelow
>Telspec Europe Ltd, Rochester, ME1 3QU
>Phone +44 (0)1634 687 133 extension 2346

Hello everyone,
 
I think that there may be some confusion about the SPI protocol.  The master / slave relationship is fairly well described in the previous parts of this message.  It is important that there is no particular "protocol" which governs how the master requests data from the slave.
 
There must be some event that tells the master that the slave has valid data which is ready to be transmitted.  This signal can be something like the slave asserting an I/O pin that is connected to an interrupt line of the master.
 
The Master SPI could also just poll the slave every so often with the understanding that $00 is a null byte and just to treat it was a "no data available" indication.
 
 
Another point, the 68332 (or QSPI really) has 4 PCS lines that can be used as peripheral chip selects.  The state of these lines are controlled by the command RAM.  This allows 4 SPI periperals to be connected together.  (One CS line per peripheral.)  In addition, the 4 PCS lines can be used to drive a 1 or 16 selector and then there can be 16 SPI peripherals.
 
Anyway, this is just a little more information.
 
Regards,
 
Charlie

-----Original Message-----
From: jeffrey.tenney@... [mailto:jeffrey.tenney@...]
Sent: Thursday, October 10, 2002 11:45 AM
To: 68300@yahoogroups.com
Subject: Re: [68300] QSPI - Can it do this?



Robert,

Your understanding of the master/slave relationship is correct.  The master
always generates the clock and the CS during any transaction.  Transactions
are full duplex, but usually the peripheral utilizes the SPI connection
only half duplex.  Like in your example, the transaction begins with two
8-bit transfers (or one 16-bit transfer if the peripheral is fast) where
only MOSI is meaningful.  The next N transfers use only MISO because you're
just reading data from the peripheral.  I've used some peripherals that
employ true full-duplex communication.  It got a little tricky at times.

SPI peripherals (ie, slaves) have specs for the required wait time between
sequential transfers while CS remains asserted.  This wait time allows the
peripheral to get ready for the next transfer, during which the peripheral
may have to provide data.  Good peripherals allow continuous transfers with
no wait time;  I guess they're just fast.  The CPU32 programs the QSPI with
the delay time (DTL in SPCR1) and other important factors.

As for the master determining the end of the transfer, the software on the
master must know what it is requesting and how many transfers' worth of
data to expect.  So the CPU32 *does* have to know how many bytes there are
to be transferred.  What's great about the QSPI is that you can simply set
up the entire transaction (multiple SPI transfers) all at once.  When it's
done, you'll have your data waiting in the QSPI Rx area.

Jeff





"Robert Manktelow" <robert.manktelow@...> on 10/10/2002 08:57:28
AM

Please respond to 68300@yahoogroups.com

To:    "Yahoo 68300 group" <68300@yahoogroups.com>
cc:
Subject:    [68300] QSPI - Can it do this?


Hello All
This is a general question about SPI operation, and QSPI on the CPU32 in
particular.

The Set-up
The CPU32 is SPI master and there is one slave. As I understand it the
CPU32
is therefore responsible for generating both the SPI clock and the chip
select for the slave throughout the transaction.

The transaction sequence is the CPU asks for information from the slave, by
sending two bytes to it, which define the request. Chip Select, SPI clock
and the DO are toggled by the CPU32 to achieve this - so far all is well.
The slave has to first decode the request and then respond by sending back
a
number of bytes, dependant on the request sent.

My question is:-
How is the slave's response data transferred into the CPU32?
The problem I have is that the CPU32 does not know when the response data
is
likely to start or how many bytes there are to be transferred.
Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
slave's chip active and drive the SPI clock during this "read" part of the
transaction.

Cheers
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346



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[Non-text portions of this message have been removed]

Robert,
 
I think from reading the prior emails, you probably understand that the SPI master DOES NOT KNOW when the slave has data ready.  You have to make up your own protocol.  Many schemes involve the processor just polling the slave SPI by sending a byte of "null" data and then looking at what the slave sent back.
 
Also, on a different topic, many people think that they should poll the SPIF flag to indicate when the last byte has been transmitted.  This is no a good thing to do.  The SPIF flag indicates that another byte can be written to the Transmit Data Register, NOT the transmit shifter.  So, as soon as the last byte of data is delivered from the Transmit Data Register to the Transmit Shifter, the SPIF flag sets.  However, the data is still shifting.  If the SPE bit is cleared by software, the byte being currently transmitted will get truncated.
 
So, the moral of this storey is that you should poll the SPE bit to determine when all activity from the SPI is completed.  (The bit self clears when the transmission is finished.)
 
Charlie

-----Original Message-----
From: Robert Manktelow [mailto:robert.manktelow@...]
Sent: Thursday, October 10, 2002 10:57 AM
To: Yahoo 68300 group
Subject: [68300] QSPI - Can it do this?


Hello All
This is a general question about SPI operation, and QSPI on the CPU32 in
particular.

The Set-up
The CPU32 is SPI master and there is one slave. As I understand it the CPU32
is therefore responsible for generating both the SPI clock and the chip
select for the slave throughout the transaction.

The transaction sequence is the CPU asks for information from the slave, by
sending two bytes to it, which define the request. Chip Select, SPI clock
and the DO are toggled by the CPU32 to achieve this - so far all is well.
The slave has to first decode the request and then respond by sending back a
number of bytes, dependant on the request sent.

My question is:-
How is the slave's response data transferred into the CPU32?
The problem I have is that the CPU32 does not know when the response data is
likely to start or how many bytes there are to be transferred.
Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
slave's chip active and drive the SPI clock during this "read" part of the
transaction.

Cheers
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346



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[Non-text portions of this message have been removed]

I have used SPI for bidirectional communications in a single master/
multiple slaves configuration. The master polls the slaves,
the communication using 7-bits (bits 0-6) of every byte.
Whatever the master sends is with bit 7 being 0, whatever the slave sends
is with bit 7 being a 1. Thus, the master can always see what got clocked
in every time it sends a byte to the slave - either what it sent last, 
if bit 7 is 0, or some output from the slave, if bit 7 is a 1. Polling
has to be limited to a rate the slaves can handle (probably they have
to do an for IRQ every byte). I have done this between a 68340 (bit-banging
the SPI) and a variable number of HC11-s. Works fine until today. 

Dimiter

------------------------------------------------------------------------
Dimiter Popoff
http://transgalactic.freeyellow.com

Hello All

Thanks you all very much for your replies.
I have implemented your suggestions and now have bi-directional SPI
communications - yes!

The key part of the jigsaw puzzle I was missing, which you all helpfully
filled in, was the requirement to transmit the correct number of "dummy"
 in my case all '0') bytes after the QSPI request bytes to enable the slave
to send back it's response.
The SPI slave I was having trouble with is a telecom line interface chip, so
there is no possibility of implementing a higher level protocol on it but,
as I know the length of the slave's response, to any request made, I can
achieve my aim's.

The QSPI is a powerful, if understated, beast. I only recently appreciated
that you can configure the individual polarity of each of the four SPI chip
selects, a feature that enables us add an SPI EEPROM that has an active high
chip select, the line interface chip being active low chip select.

Thanks
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346