68300

Hello All
This is a general question about SPI operation, and QSPI on the CPU32 in
particular.

The Set-up
The CPU32 is SPI master and there is one slave. As I understand it the CPU32
is therefore responsible for generating both the SPI clock and the chip
select for the slave throughout the transaction.

The transaction sequence is the CPU asks for information from the slave, by
sending two bytes to it, which define the request. Chip Select, SPI clock
and the DO are toggled by the CPU32 to achieve this - so far all is well.
The slave has to first decode the request and then respond by sending back a
number of bytes, dependant on the request sent.

My question is:-
How is the slave's response data transferred into the CPU32?
The problem I have is that the CPU32 does not know when the response data is
likely to start or how many bytes there are to be transferred.
Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
slave's chip active and drive the SPI clock during this "read" part of the
transaction.

Cheers
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346