68300

Robert,

Your understanding of the master/slave relationship is correct.  The master
always generates the clock and the CS during any transaction.  Transactions
are full duplex, but usually the peripheral utilizes the SPI connection
only half duplex.  Like in your example, the transaction begins with two
8-bit transfers (or one 16-bit transfer if the peripheral is fast) where
only MOSI is meaningful.  The next N transfers use only MISO because you're
just reading data from the peripheral.  I've used some peripherals that
employ true full-duplex communication.  It got a little tricky at times.

SPI peripherals (ie, slaves) have specs for the required wait time between
sequential transfers while CS remains asserted.  This wait time allows the
peripheral to get ready for the next transfer, during which the peripheral
may have to provide data.  Good peripherals allow continuous transfers with
no wait time;  I guess they're just fast.  The CPU32 programs the QSPI with
the delay time (DTL in SPCR1) and other important factors.

As for the master determining the end of the transfer, the software on the
master must know what it is requesting and how many transfers' worth of
data to expect.  So the CPU32 *does* have to know how many bytes there are
to be transferred.  What's great about the QSPI is that you can simply set
up the entire transaction (multiple SPI transfers) all at once.  When it's
done, you'll have your data waiting in the QSPI Rx area.

Jeff





"Robert Manktelow" <robert.manktelow@...> on 10/10/2002 08:57:28
AM

Please respond to 68300@yahoogroups.com

To:    "Yahoo 68300 group" <68300@yahoogroups.com>
cc:
Subject:    [68300] QSPI - Can it do this?


Hello All
This is a general question about SPI operation, and QSPI on the CPU32 in
particular.

The Set-up
The CPU32 is SPI master and there is one slave. As I understand it the
CPU32
is therefore responsible for generating both the SPI clock and the chip
select for the slave throughout the transaction.

The transaction sequence is the CPU asks for information from the slave, by
sending two bytes to it, which define the request. Chip Select, SPI clock
and the DO are toggled by the CPU32 to achieve this - so far all is well.
The slave has to first decode the request and then respond by sending back
a
number of bytes, dependant on the request sent.

My question is:-
How is the slave's response data transferred into the CPU32?
The problem I have is that the CPU32 does not know when the response data
is
likely to start or how many bytes there are to be transferred.
Can the QSPI in the CPU32 be set up to do this - i.e. set/maintain the
slave's chip active and drive the SPI clock during this "read" part of the
transaction.

Cheers
-
Robert Manktelow
Telspec Europe Ltd, Rochester, ME1 3QU
Phone +44 (0)1634 687 133 extension 2346



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