68300

Greetings

Due to system constraints we have need to use the
IDE interface hardware as general purpose parallel
i/o. The objective is to use the IDE's 16bit data,
3 address lines and its read and write and to
control these signals to form a i/o type
function - as-opposed-to data / address bus
memory-mapped decoding.

I am aware that this forum may only be partially
related to this subject, nevertheless I am hopeful
that someone would be able to shed further light
on this issue.

Thus far we are able to control the write process
except for:
1) i/o data writen as "0000h" does not produce a
write control signal
2) writes to address "00h" do not produce a write
signal

3) i/o read to the upper 4 (of 8) addresses
generate properly timed "write" signals.

The IDE interface chip is a CS5530A. The ATA / IDE
specification algorithm shows that drive status
and interrupts is to be read by the host before
data transfer can begin. The CS5530 datasheets are
not clear whether this requirement can be forced.

Any comments or experiences with IDE would be
greatly appreciated.

Regards
Russell Fowler

On the 68332, how do I change the chip select pulse width?

Robert E. Yablonski

Robert:
 
    You need to add wait states.  You do this by changing the DSACK field in the CSORx register for the corresponding chip select.  One wait state is equal to one system clock.
 
Regards, 

John Honnold 
Motorola SPS 

 -----Original Message-----
From: Robert Yablonski [mailto:yabo@...]
Sent: Thursday, September 26, 2002 2:08 PM
To: 68300@yahoogroups.com
Subject: [68300] Chip Select Pulse Width



On the 68332, how do I change the chip select pulse width?

Robert E. Yablonski



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