68300

John,

You can review the addressing modes (direct, indirect, absolute, etc.) of
the CPU32 in the CPU32RM, chapter 3.  However, the CPU32 does not do
"memory indirect" addressing,  meaning that an address stored in data
memory is useless until *you* load it into a register.  (The assembler
wouldn't do that for you.)

The instruction:

move.l $12345678, A1

uses absolute-long addressing.  The address $12345678 is stored as part of
the machine language of the instruction (in code memory).  The CPU32 gets
the address during the instruction fetch.  When the CPU32 is executing the
instruction, it puts $12345678 out on the address bus in a "read" cycle.
However, because the address bus is only 24 bits wide, the leading byte $12
never appears anywhere on the bus.  So all of the chip-select logic (even
the external stuff if you have any) sees only 24 bits and responds
accordingly.  Effectively, what that means is that $12345678 refers to the
same address as $FF345678.  Neither causes a bus error as long as $345678
and $34567A are valid addresses and word readable.

As an interesting side note, the upper byte of a 32-bit address can
actually have an effect on performance.  Consider the instruction:

move.w $00FFFA44, D0

which moves CSPAR0 to D0.  It is assembled with absolute-long addressing
since $00FFFA44 does not fit into a word.

However,

move.w $FFFFFA44, d0

also moves CSPAR0 to D0.  This instruction is assembled with absolute-short
addressing because $FFFFFA44 *does* fit into a word, namely $FA44.  This
instruction is smaller and faster than the absolute-long equivalent.

Jeff





John Mermigis <johnmerm@...> on 03/05/2003 04:03:07 AM

Please respond to 68300@yahoogroups.com

To:    68300@yahoogroups.com
cc:
Subject:    RE: [68300] Re: Theoretical questions



First of all thank you all Guys for your interest in my question
Actually, I did mention that this was a purely theoretical question, I have
already solved the problem using the folowing syntax
                 lea A2,_BlaBla
                 move.l (A2),A1
using this I (and everyone) can overcome the Bus error exception, but I
still I want to know it all
Now for the 24 vs 32 bit issue. Since I don't really know how indirect
access works, I suppose that when Assembler (I didn't use C at this point
neither inline assembly, only pure Assembler Code) sees (_BlaBla) loads the
_BlaBla address to a temp memory place
Should the temp memory be after past 0x00FFFFFF this could end up with Bus
error since the bus is 24 bit long (while the processor never had to know
that)
I sense something totally incorrect was said now but I can't know what.
Please help me some more
PS: By the way CPU Reference manual says nothing about direct or indirect
access to memory places when refering to the move instruction
 Melear Charles-rdph40 <charles.melear@...> wrote:Jeff,

I am just a hardware guy.  I know in the past that this ".w" vs ".l"
addressing has cropped up  and that it was solved by specifically adding
the ".l", i.e., (A0).l.

I've got to tell you, I am not a software guy and I can't write more than
just a few lines of C.  (void main void is my knowledege of C)  So, I am
not really able to address such issues as "what compiler would be crazy
enough".  I caught on to this several years ago when I reverse assembled
some code.  That is, I took the machine language and translated that back
into assembly instructions and then (with help from others) found the C
instruction that created the assembly language instruction.  Then the
original programmer did some majic that forced the compiler to always use
long word addressing which solved his/her original problem that was similar
to the one being addressed in this email thread.

This, unfortunately, is my sum total of knowledge on the subject.  I think
I am going to learn how to write C just as soon as I get time.

Regards,

Charlie



-----Original Message-----
From: jeffrey.tenney@... [mailto:jeffrey.tenney@...]
Sent: Tuesday, March 04, 2003 11:07 AM
To: 68300@yahoogroups.com
Subject: RE: [68300] Re: Theoretical questions



Charlie,

I am shocked that any assembler would default to word addressing for the
instruction example you give,

MOVE.B  #$12, (A0)

especially if you're saying that they originally did it for performance and
for the 68000.  First of all, the 68000 can't even perform that instruction
with word addressing (A0.W).  Second, on the CPU32, word addressing is
slower (and bigger) than longword addressing for that instruction because
it uses a suppressed address register to get word addressing.

What compiler or assembler is that crazy??

Jeff

<snip, snip>