Hi Charles,
Thanks a lot for your detailed reply. I am
extremely sorry for taking time to reply back. The country
code is 91 and probably you have to dial 0 as I have to
dial a 0 when I call up US.
Anyway the problem has been solved and it was due to
the type of flux used by the board assembler. The flux was
used for the microcontroller and since the XTAL was in the
vicinity, it was being affected. The flux is not very
easily detectable by the naked eye and that was the reason
that we failed to notice it prima facie.
The solution was the simplest as I just soaked the
boards in gasoline and gave them all a good sunbath. The
boards having been subject to such pampering are now well
mannered.
Anyway thanks a lot for your suggestions which have
indeed been very helpful, especially the points regarding
the stability and I will incorporate it in the next version
of the board. Somehow stability did not affect us till now
and that is the reason that we overlooked it.
Thanks & Regards,
Philip Jones,
Engineer,
R&D Department,
ID Technologies. (A division of mark elektriks)
============================================================
B1/1, Sai Sahawas Apt., \ufffd|\ufffdPhone: +91-20-4003315, 4007158
Oppo. Corporation Bank, \ufffd|\ufffdTeleFax: +91-20-5410479
Maharshi Karvenagar, \ufffd \ufffd |\ufffdEmail: development@...
Hingne (Bk), \ufffd \ufffd \ufffd \ufffd \ufffd \ufffd | www.markelektriks.com
Pune - 411052. India. \ufffd \ufffd|
============================================================
-----Original Message-----
From: Melear Charles-rdph40 <charles.melear@...>
To: "'68300@yahoogroups.com'" <68300@yahoogroups.com>
Date: Thu, 8 May 2003 06:55:51 -0700
Subject: RE: [68300] PLL not locking/ erratic xtal behavior
> Prashant,
>
> I tried to call you today (8:30 am in Austin, Texas,
> USA). I don't think I dialed the number right. Do I
> need a country code or is "91" the country code. You can
> sure tell I don't dial many international numbers.
>
> Any way, I do not believe that your problem is too
> serious.
>
> First of all, I need a little information from you.
>
> You stated in your email that everything was working but
> now, with the new production, things are NOT working.
> Now, look at one of the 68332's from the "old" production
> and one from the "new" production. I suspect that these
> parts will be different mask sets. The newest mask set
> is J30C. I suspect that these will be the parts that are
> giving you trouble. (Earlier mask sets include J66A and
> F98R) You can determine the mask number by reading the
> markings on the package. The mask set number is right
> under the Part Number.
>
> Anyway, J30C does not have quite as much drive capability
> as prior mask sets. This has more to do with the wafer
> line than the mask set but J30C is only made in one wafer
> line. In fact, mask sets are tied to specific wafer
> lines.
>
> So, there are several things to look at.
>
> 1. Do you have the "X" bit in the SYNCR register set to
> a logic 1? This controls the "divide by 2" circuit on
> the output of the internal PLL / VCO. If it is NOT a
> logic 1, change it to a logic 1 and then adjust the "Y"
> bits to get the proper frequency. In other words, if you
> are operating the 68332 system clock above 8 MHz, then
> look at the table in the 68332 manual where it gives
> divider ratios to obtain various system frequencies based
> on the X, W and Y bits. Choose a value from the right
> hand column. That is, make sure to use a value with X =
> 1.
>
> 2. Next, it is critical that you use the 3-component
> (High Stability XFC filter). If you are not using the
> High Stability Filter your circuit is going to have clock
> jitter in the PLL/VCO. The Normal Stability XFC filter
> is a singel 0.1 uf capacitor from the XFC pin to Vddsyn.
> The 3 component filter is an 18 Kohm resistor in series
> with a 0.1 uf cap between XFC and Vddsyn. In parallel
> with these two components is a 0.01 uf cap.
>
> 3. Third, you want to see if your crystal is starting
> correctly. The best way to do this is take a scope and
> monitor CLKOUT. (DO NOT monitor XTAL or EXTAL -- the
> scope will load these pins and give you crazy readings.)
>
> Since the J30C mask set does not have quite as much drive
> capability as prior mask sets, you might have to reduce
> the value (less ohms) of the series resistor in the
> external crystal circuit. Many times, the series
> resistor is around 330 Kohm. This may be too big (too
> many ohms). There should be about a 200 to 400
> millisecond delay between the application of power to the
> appearance of an 8.3 MHz signal on CLKOUT. If the series
> resistor is too small (less ohms) the 68332 may be
> overdriving the crystal and give really strange start up
> characteristics. If the series resistor is too big, the
> crystal will take a very long time to start.
>
> Anyway, check these things out and let me know your
> results. Be sure to check the mask sets. J30C is the
> only mask set in production and it will be the only one
> in production for a very long time into the future. So,
> you need to take into account the requirements of this
> mask set. That is, use the 3-component XFC filter, make
> sure the X bit = 1 and properly size the series resistor
> in the external crystal circuit.
>
> Best regards,
>
>
> Charlie
>
>
> -----Original Message-----
> From: development [mailto:development@...]
> Sent: Thursday, May 08, 2003 2:24 AM
> To: 68300@yahoogroups.com
> Subject: [68300] PLL not locking/ erratic xtal behavior
>
>
> Hi All,
> I am facing a very peculiar problem. I am working on
> 68332 with a 32.768 kHz xtal. The design was working fine
> in all the boards previously, but lately the xtal seems
> to
> going haywire.
>
> The only difference is that I have now a new set of
> boards, without any change in the crystal circuit. The
> PLL
> circuit does not lock by itself but if I place my finger
> somewhere near the xtal, it locks.
>
> It will run like that for some time but then it starts
> behaving erratically.
>
> I am using two 22pF capacitors along with a 330K
> resitor
> and the feedback resistor value is 10M. On the xtal it is
> written KDS 32.768.
>
> Any suggestions
>
> Regards,
> Prashant Alange
> R&D Department,
> ID Technologies. (A division of mark elektriks)
> =========================================================
> ===
> B1/1, Sai Sahawas Apt., | Phone: +91-20-4003315, 4007158
> Oppo. Corporation Bank, | TeleFax: +91-20-5410479
> Maharshi Karvenagar, | Email:
> development@...
> Hingne (Bk), | www.markelektriks.com
> Pune - 411052. India. |
> =========================================================
> ===
>
>
>
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RE: [68300] PLL not locking/ erratic xtal behavior
2003-05-21 by development