68300

Hello All,

Do I have a problem?

Hardware:
CPU:    68332GCPV25 (it runs at 25MHz)
RAM:    2 * BS62LV2000 (Chip-select access time = (must be)70ns)
Register:
DSACK:  0
Used-Signals:
Databus:    D0-15
Adressbus:  A1-A18
CS: CS0  (low byte)
    CS1  (high byte)

My system is running great, but there is following insecurity:

WS = 0
tcyc=39.7ns
Chip-select access time (MCU Read cycle) = (2+WS) * tcyc * tclsa(max)-tdicl(min)
Chip-select access time (MCU Read cycle) =  55.4ns

I measured the signal CS0/CS1 several time and the width seems to be stable at
80 ns (2*tcyc). According to which circumstances will the CS signal be  55.4ns?
Will it ever be? Do I really have to add a wait-state  (I am reliant on the speed).
If the CS0/CS1 drops down under 70ns, I would run in to deep problems.
Which SRAM do you guys use at 25 MHz.

Thx Ivo Strebel