68300

Ivo,

Yes, you have a problem.  You'll need one wait state (not zero) to use 70ns
memory with a 25MHz '332.

As your tool tells you, zero wait states require 55ns memory or faster.

Fast-Termination mode requires 15ns memory or faster.

For our 25MHz 683xx designs, we use Alliance parts
(http://www.alsc.com/products/fastasync.htm).  We always choose a 15nS part
so we can use Fast-Termination cycles.  Their stuff works great.

Jeff



|---------+---------------------------->
|         |           "Ivo Strebel"    |
|         |           <Ivo.Strebel@schi|
|         |           ller.ch>         |
|         |                            |
|         |           06/24/2004 07:47 |
|         |           AM               |
|         |           Please respond to|
|         |           68300            |
|         |                            |
|---------+---------------------------->
  >------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                              |
  |       To:       <68300@yahoogroups.com>                                                                                      |
  |       cc:                                                                                                                    |
  |       Subject:  [68300] Memory Access Time                                                                                   |
  >------------------------------------------------------------------------------------------------------------------------------|




Hello All,

Do I have a problem?

Hardware:
CPU:    68332GCPV25 (it runs at 25MHz)
RAM:    2 * BS62LV2000 (Chip-select access time = (must be)70ns)
Register:
DSACK:  0
Used-Signals:
Databus:    D0-15
Adressbus:  A1-A18
CS: CS0  (low byte)
    CS1  (high byte)

My system is running great, but there is following insecurity:

WS = 0
tcyc=39.7ns
Chip-select access time (MCU Read cycle) = (2+WS) * tcyc * tclsa(max)
-tdicl(min)
Chip-select access time (MCU Read cycle) =  55.4ns

I measured the signal CS0/CS1 several time and the width seems to be stable
at
80 ns (2*tcyc). According to which circumstances will the CS signal be
55.4ns?
Will it ever be? Do I really have to add a wait-state  (I am reliant on the
speed).
If the CS0/CS1 drops down under 70ns, I would run in to deep problems.
Which SRAM do you guys use at 25 MHz.

Thx Ivo Strebel




---------------------------------------------------To learn more about
Motorola Microcontrollers, please visit
http://www.motorola.com/mcu

learn more about Motorola Microcontrollers, please visit
http://www.motorola.com/mcu


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