68300

The SJA1000 allows both a programmable prescaler and bit length.  using
20.97MHz, divide by 6 (BRP = 2), and 14 time period; as an example TSEG1=6,
TSEG2=6 puts the read sample point about in the middle.  The actual values
will depend on the characteristics (length and loading) of the bus.

Jerry Green
Parker Hannifin ESD



                                                                                                                               
                      68300@yahoogroups                                                                                        
                      .com                     To:       68300@yahoogroups.com                                                 
                                               cc:                                                                             
                      06/04/2005 07:41         Subject:  [68300] Digest Number 198                                             
                      AM                                                                                                       
                      Please respond to                                                                                        
                      68300                                                                                                    
                                                                                                                               




There are 2 messages in this issue.

Topics in this digest:

      1. Clock drift
           From: Tim <Tim.Flynn@...>
      2. Re: Clock drift
           From: Tim <Tim.Flynn@...>


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Message: 1
   Date: Fri, 3 Jun 2005 10:49:18 -0600
   From: Tim <Tim.Flynn@...>
Subject: Clock drift

Hello Group ( I hope there are people still out there ),

I have an issue with clock drift with temperature. I have a -20 to
+60C 4.194 MHz crystal on a 68376 design. As I get the temperature up
to about 50 C, I start to see the CLKOUT pin frequency drop. The
normal rate is 20.45 MHz (picked for CAN reasons)
At about 50C clock out is 20.09 MHz , at 60 C -> 19.63 MHz.
This more than +/- 50 ppm spec of the crystal.
I am using a 1.5 K ohm series resistor and 22 pF load caps. I have
tried 27 pF as well.
I am using the high stability VCO filter too.

Anyone have some pointers as to how to correct this?




Tim Flynn
RMS Welding Systems
Ph.(780)955-3907
http://www.rmsweldingsystems.com



[Non-text portions of this message have been removed]



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Message: 2
   Date: Fri, 3 Jun 2005 14:22:28 -0600
   From: Tim <Tim.Flynn@...>
Subject: Re: Clock drift

Thanks to Charlie!
In my start up code for the clock (SYNCR) I had X bit = 0. A no-no @
20.45 MHz.
Changed the SYNCR value as per Charlie's recommendation and the clock
is now stable over temperature. Thanks again Charlie !
New problem! I have a choice of either 19.92 MHz or 20.97 MHz. Either
breaks my CAN communication. I'm running at 250 kbit/s. and I need to
communicate with SJA1000 CAN devices and 56F803 Freescale devices.
Anyone with CAN values that they would recommend?

On Jun 3, 2005, at 10:49 AM, Tim wrote:

> Hello Group ( I hope there are people still out there ),
>
> I have an issue with clock drift with temperature. I have a -20 to
> +60C 4.194 MHz crystal on a 68376 design. As I get the temperature up
> to about 50 C, I start to see the CLKOUT pin frequency drop. The
> normal rate is 20.45 MHz (picked for CAN reasons)
> At about 50C clock out is 20.09 MHz , at 60 C -> 19.63 MHz.
> This more than +/- 50 ppm spec of the crystal.
> I am using a 1.5 K ohm series resistor and 22 pF load caps. I have
> tried 27 pF as well.
> I am using the high stability VCO filter too.
>
> Anyone have some pointers as to how to correct this?
>
>
>


Tim Flynn
RMS Welding Systems
Ph.(780)955-3907
http://www.rmsweldingsystems.com



[Non-text portions of this message have been removed]



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