68331 PCLK frequency limit
2002-08-27 by Robert Manktelow
Hello All I am feeding a 6.5536Mhz clock (50:50 mark/space ratio) into the PCLK pin of the GPT and using the 16 bit free running TCNT counter to produce a 100Hz interrupts. This does not work using a 16.667MHz system clock. Replacing PCLK with the system clock divided by 4 (TMSK2 register bits CPR[]=000) works but of course the interrupt rate is wrong. I suspect the syncroniser & digital filter (Figure 7-2 of the Users Manual) may be filtering out the clock coming into PCLK but am unsure. Can anybody confirm my suspicions or tell me what is the maximum frequency I can feed into PCLK with a 16.667MHz system clock please. PS I must have an accurate 100Hz interrupt as the RTOS derives its time and date from this. - Robert Manktelow Telspec Europe Ltd, Rochester, ME1 3QU Phone +44 (0)1634 687 133 extension 2346